A survey of Microarchitectural Side-channel Vulnerabilities, Attacks, and Defenses in Cryptography


Level Category Sharing Attacks Requirements



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Level Category Sharing Attacks Requirements

Instruction
Multiply ■ Multiplier unit contention [6, 212] Floating point ■ FPU contention [12]
Branch ■ BTB contention [4, 126] [126] requires Intel SGX Micro-operation ■ Port contention [7]

P%&’()P%o+( [1, 149, 151, 151, 155, 238]
Cache set ■: L1 & L2, [2, 28, 32, 77, 85, 92, 101, 103, 113, 133]
[28, 51, 85, 92, 138, 176]
requires Intel SGX

Cache


  • : LLC

[28, 51, 85, 92, 138, 176]
Ev&ct)T&’( [151], P%&’()A+o%t [61]
F/012)R(/o34 [15, 90, 91, 199, 225]

  1. requires Intel TSX

Cache line ■: L1 & L2, F/012)F/012 [89], R(/o34+R(5%(12 [33]
Requires KSM

    • : LLC

Co//&4()P%o+(, Lo34)R(/o34[129]
LRU state leaking[221]
[129] requires AMD predictor

Memory Page


Cache bank ■ Bank contention [226], MemJam [139] [139] requires Intel SGX




  • Page
    TLB contention [40, 86]


DRAM bank row л
л Page Fault/Table Entry [180, 198, 207, 222] Requires Intel SGX Row bu$er contention [158]
Rambleed [123]


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