Air force 14. 1 Small Business Innovation Research (sbir) Proposal Submission Instructions
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PHASE III DUAL USE APPLICATIONS: DOE/DoD organizations can benefit from IV&V processes & tools developed for ICBM program s/w testing. The tool set & methods developed can be used for safety critical s/w in auto, civil aviation, medical, & industrial control in accordance w/standards such as RTCA DO 178C, IEC 61508, & SAE 27272. REFERENCES: 1. AFMAN 91-118, “Safety Design And Evaluation Criteria For Nuclear Weapon Systems," 18 Jan 1994, available online at: http://afpubs.hq.af.mil. 2. AFMAN 91-119, “Safety Design And Evaluation Criteria For Nuclear Weapon Systems Software”, 1 Feb 1999, available online at: http://afpubs.hq.af.mil. 3. N.G. Leveson, M.P.E. Heimdahl, H. Hildreth, and J.D. Reese. Requirements specification for process-control systems. IEEE Transactions on Software Engineering, pages 684–706, September 1994. 4. J.M. Spivy. The Z Notation: A Reference Manual. Prentice Hall, 1992. 5. Aditi Tagore, Diego Zaccai, and Bruce W. Weide, “Automatically Proving Thousands of Verification Conditions Using an SMT Solver: An Empirical, Study,” NASA Formal Methods Symposium (NFM 2012), Lecture Notes in Computer Science (LNCS) 7226, pp. 195–209, 2012. 6. Darren Cofer, Andrew Gacek, Steven Miller, Michael Whalen, Brian LaValley, and Lui Sha, A. Goodloe and S. Person (Eds.): NASA Formal Methods Symposium (NFM 2012), Lecture Notes in Computer Science (LNCS) 7226, pp. 126–140, 2012, © Springer-Verlag Berlin Heidelberg 2012. 7. Patrick Cousot, “Formal Verification by Abstract Interpretation,” NASA Formal Methods Symposium (NFM 2012), Lecture Notes in Computer Science (LNCS) 7226, pp. 126–140, 2012, © Springer-Verlag Berlin Heidelberg, 2012. 8. A. Burns, B. Dobbing, and T. Vardanega, “Guide for the Use of the Ada Ravenscar Profile in High Integrity Systems,” Technical Report YCS-2003-348, University of York, 2003. 9. J. A. Pulido, J. A. de la Puente, J. Hugues, M. Bordin, and T. Vardanega,“Ada 2005 Code Patterns for Metamodel-based Code Generation,” Ada Letters, vol. XXVII, no. 2, 2007. 10. Program Validation Ltd. Formal Semantics of SPARK. Program Validation Ltd., 1998. 11. Steve Vestal. “Assuring the correctness of automatically generated software,” AIAA/IEEE Digital Avionics Systems Conference, volume 13, pages 111–118, 1994. 12. Susan Stepney. High Integrity Compilation. Prentice Hall,1993. 13. Susan Stepney. Incremental development of a high integrity compiler: Experience from an industrial development. In Proceedings of the IEEE High Assurance Systems Engineering Workshop, 1998. 14. M. Bordin and T. Vardanega, “Correctness by Construction for High-Integrity Real-Time Systems: a Metamodel-driven Approach,” in Reliable Software Technologies - Ada-Europe, 2007. 15. M. Panunzio and T. Vardanega, “A Metamodel-driven Process Featuring Advanced Model-based Timing Analysis,” in Reliable Software Technologies- Ada-Europe, 2007. 16. Marco Panunzio and Tullio Vardanega “On Component-Based Development and High-Integrity Real-Time Systems.” 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. 17. M. Bordin, M. Panunzio, and T. Vardanega, “Fitting Schedulability Analysis Theory into Model-Driven Engineering,” in Proc. of the 20thEuromicro Conference on Real-Time Systems, 2008. 18. Berendsen, J., Jansen, D., Vaandrager, F.: Fortuna: Model checking priced probabilistic timed automata. In: Proc. QEST'10. pp. 273{281 (2010), see also http://www.prismmodelchecker.org/. 19. Xiaocheng Ge, Richard F. Paige, and John A. McDermid, “Probabilistic Failure Propagation and Transformation Analysis,” in B. Buth, G. Rabe, T. Seyfarth (Eds.): SAFECOMP 2009, LNCS 5775, pp. 215–228, 2009. Springer-Verlag Berlin Heidelberg, 2009. 20. Rouven Witt, Andrew Kennedy, Bastian Baetz, Ulrich Mohr, Nico Bucher, and Jens Eickhoff, "Implementation of Fault Management Capabilities for the Flying Laptop Small Satellite Project through a Failure-Aware System Model,” AIAA Infotech@Aerospace (I@A) Conference August 19-22, 2013, Boston, MA. 21. Hiroyuki Okamura, Tadashi Dohi, Shin’ichi Shiraishi and Mutsumi Abe, Composite Dependability Modeling for In-vehicle Networks. 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks, 978-1-4577-0375-1/11/ © 2011 IEEE. 22. “Architecture Analysis and Design Language Annex (AADL), Volume 1, Annex E: Error Model Annex,” International Society of Automotive Engineers, SAE Standard AS5506/1, June 2006. 23. Marc Pollina , Yann Leclerc , Eric Conquet , Maxime Perrotin, Guy Bois , Laurent Moss. The Assert Set Of Tools For Engineering (TASTE): Demonstrator, HW/SW Codesign, and Future, 2012 Embedded Real Time Systems Conference (ERTS 2012), Toulouse, France, available online at www.erts2012.org/Site/0P2RUC89/4A-3.pdf, also see http://www.assert-project.net/taste. 24. Mark Fewster amd Dorothy Graham, Software Test Automation. ACM Press/Addison-Wesley, 1999. ISBN 978-0-201-33140-0. 25. Eiffel Studio, http://sourceforge.net/projects/eiffelstudio/files/, http://en.wikipedia.org/wiki/EiffelStudio#Unit_and_Integration_Testing. 26. Gordon Fraser, Franz Wotawa, and Paul E. Ammann, Testing with model checkers: a survey. Software Testing, Verification and Reliability, 19(3):215–261, Wiley Interscience, 2009. 27. A Systematic Review of Model Based Testing Tool Support, Muhammad Shafique, Yvan Labiche, Carleton University, Technical Report, May 2010., available at http://squall.sce.carleton.ca/pubs/tech_report/TR_SCE-10-04.pdf. KEYWORDS: safety critical systems, software safety, software verification, high integrity systems, software testing, Nuclear Safety Cross Check Analysis, NSCCA AF141-093 TITLE: Development and Verification Tools/Processes for ASICs and FPGAs KEY TECHNOLOGY AREA(S): Nuclear Technology The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation and within the AF Component-specific instructions. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the AF SBIR/STTR Contracting Officer, Ms. Kristina Croake, kristina.croake@us.af.mil. OBJECTIVE: Innovative solutions for providing U.S. domestically-owned ASIC/FPGA testing processes/tools capabilities to certify against malicious code/electronics design that could cause unintended consequences from nuclear operational applications. DESCRIPTION: Programmable Logic Devices, such as FPGAs and ASICs, controlling U.S. nuclear weapons must have the highest possible assurance of safety and integrity. Top-level safety requirements, called Nuclear Safety Objectives (NSOs), for such devices are set forth in two publications, AFMAN 91-118 and 91-119 (see references). Additional specific functional and non-functional requirements are developed for the specific devices at the start of the development. A specialized process must be used for intensive verification of system safety against these and other derived requirements.
As ASICs and FPGAs grow increasingly complex; the nuclear surety certification process must innovate to provide modernized processes and tools and to assure their correctness, safety, and integrity to maintain the highest level of safety. The RTCA DO 254 standard (see references) developed for complex programmable logic devices in avionics applications has also been used in other applications and is an industry and certification authority accepted approach for assuring conformance with safety requirements. For nuclear weapons applications, the anticipated assurance level would be System Level A. The objective of this research is to define a high assurance process and associated tool set to provide this assurance. The specific goals include: 1. A gap analysis of the RTCA DO 254 standard against AFMAN 91-118, 91-119, AFI 91-101 requirements and recommendations for changes (if any). 2. Definition of a specific set of process objectives and verification criteria for device assurance. 3. Identification of specific tools or definition of methods to actualize the process. It is anticipated that such tools will include: b. HDL tools (VHDL, Verilog, or SystemC) for design and testbench synthesis c. Functional simulation d. Logic synthesis e. Logic equivalency checking f. Place and route g. Worst-case timing analysis h. Other special analytical capabilities Proposals that describe solutions utilizing existing tools, or new tools, or both, to achieve these capabilities in a single integrated framework are encouraged. PHASE I: Demonstrate the feasibility of a methodology and associated tools to Nuclear Safety Cross-Check Analysis (NSCCA) verification. PHASE II: Full development (and testing) of the tools and demonstrate the methodology proposed on realistic representative test cases. PHASE III DUAL USE APPLICATIONS: Broaden tool for safety critical software in auto, civil aviation, medical and industrial control in accordance with standards (RTCA DO 254). Processes/tools may also be used to protect against malicious programming of ASIC/FPGA devices used by commercial industry and to detect counterfeit parts. REFERENCES: 1. AFMAN91-118, Safety Design and Evaluation Criteria for Nuclear Weapon Systems, 18 Jan 1994, available online at: http://afpubs.hq.af.mil. 2. AFMAN 91-119 , Safety Design And Evaluation Criteria For Nuclear Weapon Systems Software, 1 Feb 1999, available online at: http://afpubs.hq.af.mil. 3. RTCA DO-254/ED-80 (Design Assurance Guidance for Airborne Electronic Hardware), RTCA, Inc.1828 L Street, NW, Suite 805Washington, D.C. 20036 U.S.A (202)833-93. KEYWORDS: safety critical systems, ASICs, FPGAs, safety critical, verification, validation, formal methods, testing AF141-094 TITLE: Algorithm Based Error Estimation & Navigation Correction KEY TECHNOLOGY AREA(S): Electronics and Electronic Warfare The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation and within the AF Component-specific instructions. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the AF SBIR/STTR Contracting Officer, Ms. Kristina Croake, kristina.croake@us.af.mil. OBJECTIVE: Develop and demonstrate an algorithm-based scheme that improves navigation accuracy and responsiveness of inertial-based navigation systems. DESCRIPTION: The U.S. Air Force would like to explore more accurate and more robust navigation capabilities for strategic systems. The strategic system is heavily dependent on the Inertial Measurement Unit (IMU) for strategic system navigation since there is limited or no external aiding. Whereas the Navy’s SLBM uses a star tracker to aid its inertial navigation system, the Air Force ICBM mission relies entirely on autonomous inertial navigation. The Air Force would like to explore improving accuracy without having to implement an external aiding scheme to the ICBM navigation, guidance and control system. Since computing power has drastically increased over the past decades, the Air Force is interested in complimenting strategic grade inertial sensors with advanced navigation algorithms to improve performance during flight. With the exclusion of external aiding, the current and future hardware must have a complimentary suite of navigation algorithms to ensure the strategic vehicle will meet the desired terminal conditions.
PHASE I: Develop algorithms for an IMU-based navigation system that addresses nonlinear, non-Gaussian error terms encountered during system flight. Describe the trade-offs, and develop concepts of operations for different alternatives developed. Prepare a report on the findings and develop a plan to demonstrate the navigation algorithms in a relevant simulation environment. PHASE II: Develop a demonstration of the algorithms using realistic IMU models, demonstrating the ability of the algorithms to accurately navigate an ICBM or CM (without updates) to within a prescribed set of targeting conditions. Evaluate the feasibility of transitioning these capabilities into flight capable hardware, including integration into different missile systems. PHASE III DUAL USE APPLICATIONS: This technology, if realized, would be of obvious immediate benefit to both DoD and commercial IMU users operating in a GPS-denied environment, such as buildings. REFERENCES: 1. (Removed by TPOC 12/3/13.) 2. (Removed by TPOC 12/3/13.) 3. (Removed by TPOC 12/3/13.) 4. (Removed by TPOC 12/3/13.) 5. Brown and Hwang; Introduction To Random Signals and Applied Kalman Filtering, 3rd Ed.; Wiley 1997 6. Kenneth R. Britting; Inertial Navigation Systems Analysis, Artech House 2010 7. Anton J. Haug; Bayesian Estimation and Tracking: A Practical Guide; Wiley & Sons, Inc. 2012 KEYWORDS: navigation, algorithm, error correction, statistical, dynamic constraints, Bayesian, nonlinear estimation, inertial based navigation, strategic system navigation, GPS denied navigation algorithms, nonlinear navigation schemes AF141-096 TITLE: Radiation Hardened Cache Memory KEY TECHNOLOGY AREA(S): Materials / Processes The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation and within the AF Component-specific instructions. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the AF SBIR/STTR Contracting Officer, Ms. Kristina Croake, kristina.croake@us.af.mil. OBJECTIVE: Develop a power efficient, high speed, radiation hardened memory device suitable for long term space missions by using carbon nanotubes (CNT) or other innovative materials and processes, (e.g.graphene), processes (3-D), & architectures (memristive). DESCRIPTION: In order to meet projected growth in broadband military satellite communications, future generations of payloads will be required to process the waveform at a significantly higher rate. Unacceptably long memory cycle times can diminish the performance of payload front-end processing by adding undesirable time lags and leading to poor overall payload performance. To address this concern, the Air Force seeks a new generation of radiation hardened cache memory devices capable of allowing the central processing unit (CPU) to operate with minimum memory cycle time by avoiding the introduction of wait states. Before the next generation cache memory is viable for insertion into a space mission, the materials and/or fabrication process must be proven reliable, affordable, and of a density and performance that makes the memory component attractive as an alternative to the current generation of space memory. In particular, the cache memory device must be shown capable of meeting the timing constraints of an emerging generation of space qualified general purpose and special purpose processors, while withstanding the full range of natural and manmade threats encountered in a long term, geosynchronous space environment. The purpose of this topic is to support research into innovative materials and/or processes leading to a high speed cache memory device. In order to better cope with the complex radiation environments, spacecraft electronics are often implemented in a “radiation-hardened” form that is three or more generations behind the contemporary commercial state-of-the-art. Since spacecraft are furthermore power-constrained, the effects of these performance penalties are compounded by an inability to field enough of the slower components to mitigate this gap. Component selections are limited, especially for specialty memories, which stand-alone cache (e.g., “level 2” or “L2”) are considered to be. Despite the compelling benefits that effective cache architectures can provide to general- purpose computation, much less attention is paid in developing these options as in developing the processor or FPGA components that might take advantage of them. In this topic, we seek creative innovations that will give us better options for larger, lower-power, and higher-performance (measured in reduced average access delays from processors) memory components that can either augment a traditional memory hierarchy or effectively collapse it (for example, by having a L2 cache large enough to fit most problems of interest without having cache miss events). The answer need not be confined to a traditional component solution, but can involve new interpretations of hybrid memory, stacked components (for example, using through-silicon vias), even possibly three-dimensional architectures that more effectively collocate processing resources with larger, more efficient memory structures. It may be advantageous to examine new architectural approaches, such as memristors, and materials, such as carbon nanotubes, phase-change materials, or grapheme. Along with these notions of better memory technologies, we must overlay the considerable constraints of working in space. Before the next-generation cache memory is viable for insertion into a space mission, the materials and/or fabrication process must be proven reliable, affordable, and of a density and performance that makes the memory component attractive as an alternative to the current generation of space memory. In particular, the cache memory device must be shown capable of meeting the timing constraints of an emerging generation of space-qualified general purpose and special purpose processors, while withstanding the full range of natural and manmade threats encountered in a long-term, geosynchronous space environment. And of course, the cost of modern microelectronics fabrication provides a challenge as great as most of the other technical barriers. Example goals include access time < 3 ns, density >> 16 Mbits, simple voltage supply (e.g., < 3.3V or configurable power rail), extended operating temperature range (-40 to +80 degrees C), 1 Mrad(Si) total dose radiation tolerance, and Single Event Effect (SEE) immunity to 60 MeV. Commercial applications include consumer electronics, auto, and commercial space. PHASE I: Investigate design architecture trade-offs and process integration issues concerned with developing radiation-hardened cache memory. Establish feasibility of a next-generation cache concept through as many methods as practical, to include simulation models, reference designs, and prototyping (may be useful in approaches involving advanced materials and devices). PHASE II: Develop one or more prototypes and characterize for access time, radiation tolerance from total dose and single event effects, storage density, and power consumption. We encourage offerors to seek partnerships with suitable semiconductor houses for assistance with fabrication support, along with the sponsorship of aerospace contractors / developers to improve technology transition opportunities. PHASE III DUAL USE APPLICATIONS: Military applications for radiation hardened cache memory include spacecraft avionics for satellite bus subsystems and payloads. Commercial: Commercial spacecraft can benefit directly from this work. REFERENCES: 1. S. Manne, A. Klauser, and D. Grunwald, “Pipeline gating: speculation"; J. Abella and A. Gonzalez, “Heterogeneous way-size cache,” in ICS, 2006. 2. D. H. Albonesi, “Selective cache ways: on-demand cache resource allocation,” in MICRO:, 1999. 3. L. Chen, X. Zou, J. Lei, and Z. Liu, “Dynamically reconfigurable cache for low-power embedded system,” in ICNC, 2007. KEYWORDS: Cache memory, radiation hardened cache, random access memory, volatile memory, carbon nanotube, cycle time, wait state AF141-097 TITLE: Next Generation Rad Hard Reduced Instruction Set Computer KEY TECHNOLOGY AREA(S): Space Platforms The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation and within the AF Component-specific instructions. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the AF SBIR/STTR Contracting Officer, Ms. Kristina Croake, kristina.croake@us.af.mil. OBJECTIVE: Develop a radiation-hardened Advanced Reduced Instruction Set Computer suitable for use in long-term space missions. DESCRIPTION: As satellite payload processing becomes more broadly distributed across subsystems, there will likely be an increased need for a new generation of smaller (relative to general purpose processors), more power efficient, radiation-hardened microprocessors of reduced complexity to meet a broad range of payload processing functions such as antenna controllers. Advanced architectures, such as the Advanced RISC (Reduced Instruction Set Computer) Machines (ARMs), are ideal candidates for distributed space processing. For example, ARMs are typically designed for: power efficiency, small circuit board footprint, limited instruction set (which eases the programmer’s learning curve), and a relatively small gate count (which reduces hardware complexity and improves reliability). In addition, the extensive commercial use of ARMs has led to a broad assortment of advanced development and debugging tools and the extensive commercial legacy providing failure data to help instill confidence for space mission assurance. The purpose of this topic is to develop a 32-bit, radiation-hardened, space-qualifiable ARM processor that is suitable for long-term space missions. Research under this topic should strive to maintain compatibility with commercial ARM processors to leverage existing software development support, including debugging tools. ARM prototypes developed under this research should also strive to include a full complement of built-in features, including interrupt controller, optimized gate count, power-saving mode, debug capability, 32-bit word length, and fully deterministic timing behavior. Additional goals include immunity to destructive latchup, total ionizing dose tolerance to 1Mrad (Si), Single Event Effect (SEE) immunity to 60 MeV, operating temperature range from -40° C to +80° C, and component reliability consistent with 15-year on-orbit satellite mission life. Directory: wp-content -> uploads -> 2016 2016 -> 2017 afoCo Landmark Scholarship Program 2016 -> Instructions for the Preparation of Camera-Ready Contributions to the Conference Proceedings 2016 -> Step student Scholarships for Year 10-13 2016 -> The united church of canada 2016 -> Idan raichel biography – May 2016 Brief Producer, keyboardist, Lyricist, composer and Performer Idan Raichel 2016 -> An introduction to centre’s interventions expanding access to justice 2016 -> Sanchar Shakti 2016 -> Unit analysis should help here. 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