M. Y. Bogatyrev, O. Y. Zolotykh, A.N. Kozlov, V.A. Usov ON APPLYING GENETIC PROGRAMMING TO DATABASE SOFTWARE ANALYSIS AND DESIGN

M. Y. Bogatyrev, O. Y. Zolotykh, A.N. Kozlov, V.A. Usov ON APPLYING GENETIC PROGRAMMING TO DATABASE SOFTWARE ANALYSIS AND DESIGN

In this paper three special fields of implementing GP in database software analysis and design have been considered. They are Client - Server RDBMS Performance Optimization, Database Software Testing, and Automated Software Generating. The possibility of integrating these various fields of information technologies under single approach is theoretically based on nature of genetic algorithms and genetic programming. Practical way of realizing the approach using Oracle database procedures is considered.

1. 
   John R. Koza. Genetic Programming: On the Programming of Computers by Natural Selection. MIT Press, Cambridge, MA, USA, 1992.
   
2. 
   D. E. Goldberg. Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley, Reading, MA, 1989.
   
3. 
   C. Billings, M. Billings, J. Tower Rapid Application Development with Oracle Designer/2000 - Addison-Wesley, 1997.
   

L.I. Volgin, A.B. Climovsky RELATOR HARDWARE OF SORTING NETWORKS

At solution of a set of tasks of conversion and processing of the multivariate information the researched object is described as an array of signals, the components of which can be depending on time. It is often necessary to present this array as a sequence of signals ordered according to some key. If the signal strength (value of component of vector) is selected as information key, then the ordered sequence is named a variational set . The conversion of input array into variational set can be fulfilled by the sorting processor (or sorting network). In relators circuitry (also in comparator circuitry [1]) such network will be naturally to consist of minimax devices, in which are being compared pairly all elements of input array [2]. For minimax devices the optimum network, which fulfils insert algorithm, is based on properties of the Pascal graph [3]. After connecting of graphs in an amount n by output nodes and at feeding of component of input vector with number "i" into a input site (node) of the graph with number "i" the composite graph, consisting from n of stratums (each of which represents the Pascal graph), will be created. This composite graph reproduces the operation of complete sorting of all n components of an input array [4,5].

At hardware implementation of the network, being reproduction the one Pascal graph (one stratum of the composite graph) for n-dimensional vector, by multichannel relators for optimum network comparators and switches are necessary. For hardware implementation of the sorting relator network (composite graph from n of stratums) is necessary amount of units more in of n times - of comparators and of switches accordingly.

The obtained network is unoptimum in control and, therefore, is redundant in hardware. In the circuit with optimum control implemented in circuitry of multichannel relators is required twice less of comparators - (at sorting of components of a n-dimensional vector). It is reached by recontrol of switches with the purpose of exception of repeated comparing. Thus the comparator controls switches locating earlier in different levels in stratums of the initial multilayer graph. It reduces and to optimization of load of comparators too. In the obtained structure each comparator controls by switches.

The operation of comparing of all array components of analog signals is carried out according to a principle "everyone with all". As the network is constructed on separate relators, the network is naturally structured along vertical (parallel) and horizontal channels of information processing. The changing of a status of switches (the setting of required structure of connections of switches again) in relator networks is carried out for one clock tick. Along horizontal channels the switches of relators are located sequentially.

Therefore, in a general case, with full comparing, time of processing at usage of a principle "everyone with all" is , where is an aggregate delay imported by a comparator and a switches on its controlling input, – delay imported by one switch at passing of a signal through this switch. In a extreme case in relator networks the all time of conversion can be diminished up to minimum, which is a time delay in one relator and is equal one clock tick. For a case of, and initial sorting network, and sorting network with optimum control, the time of processing is accepting an intermediate value .

1. 
   Knuth D.E. The art of computer programming. Vol.3 Sorting and searching, AWPC, 1973.- 848 p.
   
2. 
   Volgin L.I. Synthesis of devices for processing and conversion of the information in element base of relators .- of Tallinn: Valgus, 1989.-180 p. (in Russian).
   
3. 
   Volgin L.I. Structural properties of the Pascal graph // Relator and continuously-logic networks and models: Works of international scientific and technical conference "Neural, relator and continuously-logical networks and models".- 1998.- Vol.2.- p.13-17. (in Russian).
   
4. 
   Climovsky A.B. The relator processor of ranking // Works of international scientific and technical conference "Methods and means of conversion and processing of the analog information".- 1999, - Vol.2.- p. 34-35. (in Russian).