CS316 Autumn 2013 2014 C. Kozyrakis
Part D with the static branch predictor of Part C
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| Part D with the static branch predictor of Part C.
4. [4 points] Argue whether the Two-level Adaptive Branch Prediction Scheme [Yeh & Patt]
This problem will help you understand the details of scheduling and management in a micro-dataflow example. The Metaflow architecture was first implemented in the Sparc Lightning processor to help exploit instruction-level parallelism [Popescu et al. IEEE Micro 1991]. The architecture utilizes an interagted instruction-shelving (DRIS) structure to execute instructions out of order. To exploit instruction-level parallelism while maintaining consistency, the DRIS forms a unified structure for register renaming, dependency checking, result forwarding, and ROB. In this problem, you will explore the details of the DRIS structure and understand how it functions by tracking the state of the DRIS through a sample code trace. The DRIS entry parameters and operations are explained in the IEEE Micro1991 paper distributed along with this assignment. To simplify the problem, we are going to trace the execution of the Metaflow processor abstractly. For step 1, show the state of the DRIS after you have issued the instruction trace (from PC=101 to PC=111) into DRIS starting with entry 1. In step 2, show the state of DRIS after all instructions that are ready to execute at the end of step 1 have been executed and their results forwarded the appropriate locations in DRIS. In step 3, show the state of the DRIS and register file after all instructions that are ready to complete at the end of step 2 have been retired. In the subsequent steps, repeat the operations in step 2 and 3 until all instructions have retired out of the DRIS. You can attach extra tables if necessary. Note: don’t forget to consider memory dataflow dependences of load and store instructions. Also, assume load and store addresses are in register indirect format and thus do not require separate computation. Branch instructions are predicted not taken at first so the execution proceeds down the sequential path speculatively until the branch is resolved. Assume no internal memory by-passing, i.e loads and store must go to memory. PC= 101: mul r1, r1, r3 ; r1 r1 * r3 102: add r3, r1, r2 ; r3 r1 + r2 103: sub r4, r4, r2 ; r4 r4 – r2 104: sw (r4), r1 ; mem[r4] r1 105: mul r1, r2, r4 ; r1 r2 * r4
; if r1 != r4 109: sub r2, r2, r4 ; r2 r2 – r4 110: mult r3, r1, r3 ; r3 r1 * r3 111: add r4, r3, r1 ; r4 r3 + r1 …………..
115: halt Step 1 Register File
DRIS
Note:
Use {add, sub, mul, br, lw, and sw} for the function unit column. In this problem, the dispatch column is effectively the same as the executed column and do not need to be filled. Step 2 Register File
DRIS
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