Opcode fetch machine cycle of 8085

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  Each instruction of the processor has one byte opcode.
  
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  The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.
  
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  Hence, every instruction starts with opcode fetch machine cycle.
  
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  The time taken by the processor to execute the opcode fetch cycle is 4T.
  
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  In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
  

Ex: (1) ORA A (2) ANI B, 01H

Ex: (1) CALL (2) JMP 4100

Ex: (1) NOP (2) END

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  Every instruction of a program has to operate on a data.
  
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  The method of specifying the data to be operated by the instruction is called Addressing.
  
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  The 8085 has the following 5 different types of addressing.
  

               2. Direct Addressing

               3. Register Addressing

               4. Register Indirect Addressing

               5. Implied Addressing
1. Immediate Addressing:

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  In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction.
  
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  EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H.
  

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  In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory.
  
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  EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H
  

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  In register addressing mode, the instruction specifies the name of the register in which the data is available.
  
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  EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.
  

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  In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair.
  
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  EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.
  

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  In implied addressing mode, the instruction itself specifies the data to be operated.
  
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  EX. CMA - Complement the content of accumulator; RAL
  

LOGICAL INSTRUCTIONS

CONTROL INSTRUCTIONS

Opcode	Operand	Explanation of Instruction	Description
NOP	none	No operation	No operation is performed. The instruction is fetched and decoded. However no operation is executed. Example: NOP
HLT	none	Halt and enter wait state	The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT
DI	none	Disable interrupts	T the interrupt enable flip-flop is reset and all the in teinterrupts except the TRAP are disabled. No flags are afaffected. Example: DI
EI	none	Enable interrupts	The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction is necessary to reenable the interrupts (except TRAP). Example: EI
RIM	none	Read interrupt mas	This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM
SIM	none	Set interrupt mask	This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM

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  The memory read machine cycle is executed by the processor to read a data byte from memory.
  

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  The processor takes 3T states to execute this cycle.
  
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  The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.
  

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  The memory write machine cycle is executed by the processor to write a data byte in a memory location.
  
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  The processor takes, 3T states to execute this machine cycle.
  

LXI H 4000H : HL points 4000H

MOV A, M : Get first operand

INX H : HL points 4001H

ADD M : Add second operand

INX H : HL points 4002H

MOV M, A : Store result at 4002H

HLT : Terminate program execution

LXI H 4000H : HL points 4000H

MOV A, M : Get first operand

INX H : HL points 4001H

SUB M : Subtract second operand

INX H : HL points 4002H

MOV M, A : Store result at 4002H

HLT : Terminate program execution

time and unit states.

I/O STRUCTURE OF A TYPICAL MICROCOMPUTER:

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  Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O port and controlled by software.
  
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  Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor, and initiate data transfer.
  
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  Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can be performed by bypassing the microprocessor.
  

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  The input device will load the data to the port.
  
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  When the port receives a data, it sends message to the processor to read the data.
  
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  The processor will read the data from the port.
  
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  After a data have been read by the processor the input device will load the next data into the port.
  

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  The processor will load the data to the port.
  
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  The port will send a message to the output device to read the data.
  
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  The output device will read the data from the port.
  
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  After the data have been read by the output device the processor can load the next data to the port.
  
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  The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755.
  
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  8212
  
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  The 8212 is a 24 pin IC.
  
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  It consists of eight number of D-type latches.
  
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  It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
  
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  The 8212 can be used as an input or output device
  
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  It has two selecting device DS1 (low) and DS2.
  

8155:

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  It has two numbers of 8-bit parallel I/O port (port-A and B)
  
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  One number of 6-bit parallel I/O port (port-C).
  
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  It has 14 bit timer (operating in 4 modes).
  
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  It has six internal addresses.
  
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  It has one chip select pin CS (low).
  

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  It has two numbers of 8-bit parallel I/O port (port-A and B)
  
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  One number of 6-bit parallel 1 port (port-C).
  
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  It has 14 bit timer (operating in 4 modes).
  
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  It has six internal addresses.
  
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  It has one chip select pin CS (low).
  

Fig - Internal address of 8156

8255:

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  It has 3 numbers of 8-bit parallel I/O ports (port A, B and C).
  
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  Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port.
  
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  Port-B can be programmed in mode-1 and mode-2 as 1/Oport.
  
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  When ports A and B are in mode-0, the port-C can be used as I/O port.
  
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  One logic low chip select (CS) pin.
  
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  It requires four internal addresses
  

8355:

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  It has 2KB ROM.
  
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  It has two number of 8 bit port (A,B).
  
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  It has one CS(low).
  
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  It has four internal addresses.
  

8755:

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  It has 2Kb EPROM.
  
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  It has two number of 8 bit port (A,B).
  
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  It has one CS(low).
  
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  It has four internal addresses.
  

Fig - Internal address of 8255

HARDWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY INTERFACE

Fig. shows the multiplexed eight 7-segment display connected in the 8085 system using 8255. In this circuit port A and port B are used as simple latched output ports. Port A provides the segment data inputs to the display and port B provides a means of selecting a display position at a time for multiplexing the displays. A0-A7 lines are used to decode the addresses for 8255. For this circuit different addresses are:

PA = 00H PB = 01H

PC = 02H CR = 03H.

The register values are chosen in Fig. such that the segment current is 80 mA. This current is required to produce an average of 10 mA per segment as the displays are multiplexed. In this type of display system, only one of the eight display position is 'ON' at any given instant. Only one digit is selected at a time by giving low signal on the corresponding control line. Maximum anode current is 560 mA (7-segments x 80 mA = 560 mA), but the average anode current is 70 mA.

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  A typical semiconductor memory IC will have n address pins, m data pins (or output pins).
  

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  Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).
  

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  The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).
  

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  The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable).
  

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  2-4 decoder (74LS139)
  

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  3-8 decoder (74LS138)
  

Introduction to programmable Peripheral Interface 8255 – Pin Diagram – Architecture – Modes of Operation: I/O and BSR – Architecture and operation of 8251 (USART).

The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.

The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports.

The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 8255.