Universal Serial Communication Interface – uart mode



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1.4.3 UCBxBR0 Register


USCI_Bx Baud Rate Control Register 0
1-19. UCBxBR0

7




6

5

4




3

2

1

0
















UCBRx













rw




rw

rw

rw




rw

rw

rw

rw

Can be modified only when UCSWRST = 1.


Bit

Field

Type

Reset

Description

7-0

UCBRx

RW

undefined

Bit clock prescaler high byte. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value UCBRx.
Table 1-5. UCBxBR0 Register Description

Bit

Field

Type

Reset

Description

7-0

UCBRx

RW

undefined

Bit clock prescaler low byte. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value UCBRx.

1.4.4 UCBxBR1 Register


USCI_Bx Baud Rate Control Register 1

Figure 1-20. UCBxBR1 Register

7




6

5

4




3

2

1

0
















UCBRx













rw




rw

rw

rw




rw

rw

rw

rw

Can be modified only when UCSWRST = 1.

Table 1-6. UCBxBR1 Register Description

1.4.5 UCBxSTAT Register


USCI_Bx Status Register
1-21. UCBxSTAT

7

6

5

4

3

2




1

0

Reserved

UCSCLLOW

UCGC

UCBBUSY







Reserved







rw-0

r-0

rw-0

r-0

r0

r0




r0

r0

Table 1-7. UCBxSTAT Register Description

Bit

Field

Type

Reset

Description

7

Reserved

RW

0h

Reserved. Always reads as 0.

6

UCSCLLOW

R

0h

SCL low

0b = SCL is not held low.

1b = SCL is held low.


5

UCGC

RW

0h

General call address received. UCGC is automatically cleared when a START condition is received.

0b = No general call address received

1b = General call address received


4

UCBBUSY

R

0h

Bus busy

0b = Bus inactive



1b = Bus busy

3-0

Reserved

R

0h

Reserved. Always reads as 0.

1.4.6 UCBxRXBUF Register


USCI_Bx Receive Buffer Register

Figure 1-22. UCBxRXBUF Register

7




6




5

4




3

2

1

0



















UCRXBUFx













r




r




r

r




r

r

r

r

Table 1-8. UCBxRXBUF Register Description

Bit

Field

Type

Reset

Description

7-0

UCRXBUFx

R

undefined

The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCBxRXBUF resets UCRXIFG.

1.4.7 UCBxTXBUF Register


USCI_Bx Transmit Buffer Register

Figure 1-23. UCBxTXBUF Register

7




6

5

4

3

2

1

0













UCTXBUFx













rw




rw

rw

rw

rw

rw

rw

rw

Table 1-9. UCBxTXBUF Register Description

Bit

Field

Type

Reset

Description

7-0

UCTXBUFx

RW

undefined

The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCTXIFG.

1.4.8 UCBxI2COA Register USCIBx I2C Own Address Register

Figure 1-24. UCBxI2COA Register

15

14

13

12

11

10

9




8

UCGCEN







Reserved










I2COAx




rw-0

r0

r0

r0

r0

r0

rw-0




rw-0

7

6

5

4

3

2

1




0










I2COAx
















rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0




rw-0

Can be modified only when UCSWRST = 1.


Bit

Field

Type

Reset

Description

15-10

Reserved

R

0h

Reserved. Always reads as 0.

9-0

I2CSAx

RW

0h

I2C slave address. The I2CSAx bits contain the slave address of the external device to be addressed by the USCI_Bx module. It is only used in master mode. The address is right justified. In 7-bit slave addressing mode, bit 6 is the MSB and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB.
Table 1-10. UCBxI2COA Register Description

Bit

Field

Type

Reset

Description

15

UCGCEN

RW

0h

General call response enable

0b = Do not respond to a general call



1b = Respond to a general call

14-10

Reserved

R

0h

Reserved. Always reads as 0.

9-0

I2COAx

RW

0h

I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right justified. In 7-bit addressing mode, bit 6 is the MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB.

1.4.9 UCBxI2CSA Register USCI_Bx I2C Slave Address Register

Figure 1-25. UCBxI2CSA Register

15

14

13




12




11

10

9




8










Reserved
















I2CSAx




r0

r0

r0




r0




r0

r0

rw-0




rw-0

7

6

5




4




3

2

1




0
















I2CSAx
















rw-0

rw-0

rw-0




rw-0




rw-0

rw-0

rw-0




rw-0

Table 1-11. UCBxI2CSA Register Description

1.4.10 UCBxIE Register


USCI_Bx I2C Interrupt Enable Register
1-26. UCBxIE

7




6

5

4

3

2

1

0




Reserved




UCNACKIE

UCALIE

UCSTPIE

UCSTTIE

UCTXIE

UCRXIE

r-0




r-0

rw-0

rw-0

rw-0

rw-0

rw-0

rw-0

Table 1-12. UCBxIE Register Description

Bit

Field

Type

Reset

Description

7-6

Reserved

R

0h

Reserved. Always reads as 0.

5

UCNACKIE

RW

0h

Not-acknowledge interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


4

UCALIE

RW

0h

Arbitration lost interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


3

UCSTPIE

RW

0h

STOP condition interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


2

UCSTTIE

RW

0h

START condition interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


1

UCTXIE

RW

0h

Transmit interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


0

UCRXIE

RW

0h

Receive interrupt enable

0b = Interrupt disabled

1b = Interrupt enabled


1.4.11 UCBxIFG Register USCI_Bx I2C Interrupt Flag Register
1-27. UCBxIFG

7




6

5

4

3

2

1

0




Reserved




UCNACKIFG

UCALIFG

UCSTPIFG

UCSTTIFG

UCTXIFG

UCRXIFG

r-0




r-0

rw-0

rw-0

rw-0

rw-0

rw-1

rw-0

Table 1-13. UCBxIFG Register Description

Bit

Field

Type

Reset

Description

7-6

Reserved

R

0h

Reserved. Always reads as 0.

5

UCNACKIFG

RW

0h

Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received.

0b = No interrupt pending

1b = Interrupt pending


4

UCALIFG

RW

0h

Arbitration lost interrupt flag

0b = No interrupt pending

1b = Interrupt pending


3

UCSTPIFG

RW

0h

STOP condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received.

0b = No interrupt pending

1b = Interrupt pending


2

UCSTTIFG

RW

0h

START condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0b = No interrupt pending

1b = Interrupt pending



1

UCTXIFG

RW

0h

USCI transmit interrupt flag. UCTXIFG is set when UCBxTXBUF is empty.

0b = No interrupt pending

1b = Interrupt pending


0

UCRXIFG

RW

0h

USCI receive interrupt flag. UCRXIFG is set when UCBxRXBUF has received a complete character. 0b = No interrupt pending

1b = Interrupt pending


1.4.12 UCBxIV Register


USCI_Bx Interrupt Vector Register
1-28. UCBxIV

15




14

13




12




11

10

9

8



















UCIVx













r0




r0

r0




r0




r0

r0

r0

r0

7




6

5




4




3

2

1

0



















UCIVx













r0




r0

r0




r0




r-0

r-0

r-0

r0

Table 1-14. UCBxIV Register Description

Bit

Field

Type

Reset

Description

15-0

UCIVx

R

0h

USCI interrupt vector value

00h = No interrupt pending

02h = Interrupt Source: Arbitration lost; Interrupt Flag: UCALIFG; Interrupt Priority: Highest

04h = Interrupt Source: Not acknowledgment; Interrupt Flag: UCNACKIFG

06h = Interrupt Source: Start condition received; Interrupt Flag: UCSTTIFG 08h = Interrupt Source: Stop condition received; Interrupt Flag: UCSTPIFG

0Ah = Interrupt Source: Data received; Interrupt Flag: UCRXIFG

0Ch = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest


USB Devices

Introduction


The MSP430 makes an ideal USB device: ultra-low power, rich integration of peripherals and it’s inexpensive. Do you want to make a Human Interface Device product? Maybe a sensor, such as a barcode reader, that needs to be both low-power (when collecting data), but also capable of ‘dumping’ its data via USB to a computer. Dream big, we’ve got the devices, tools, and software to help you make them come true.

What is USB?

Universal Serial Bus (USB) is just that, a universal serial connection between a “Host” and “Device”. It has taken the place of many synchronous and asynchronous serial bus connections in systems such as personal computers.



In the case of USB, the host manages all transfers, whether moving data to or from the host – often this is called a master/slave architecture, where the host is the bus master. At a minimum, there needs to be one host and one device.

But USB supports many more than just a single device, the standard can actually support up to 127 different devices. Commonly, systems with multiple devices use hubs as interconnection points between the host and devices – which results in a star arrangement.



Each type of device is distinguished using Vendor and Product ID (VID/PID). The combination of VID and PID allows a host to identify the type of device that is connected and manage the pointto-point communications with it – in most cases, this requires the host to load the appropriate drivers required to talk with that specific type of device.

The Universal Serial Bus protocol has gone through a few versions over time. Back in 1995 USB revision 1.1 was released. This version provided separate host and device connectors along with supporting two different speeds: Low speed moved data at speeds up to 1.5Mpbs (megabits-persecond); while Full speed provided data rates up to 12Mbps.

In 2000, USB 2.0 was released as an upgrade to USB 1.1. Along with Low and Full speeds, a much faster High 480Mbps rate was added. Other major additions to the standard included a power supply of 500 mA provided from the USB cable, as well as capability for advanced devices to switch between Host and Device modes – called On-The-Go (OTG) mode. The OTG feature is handy in some applications where a product might have to be a Device or a Host depending upon what it is connected to.


USB Standards

Version

Year

Speeds

Power Available

Notes

USB 1.1

1995

1½ Mbps (Low)

12 Mbps (Full)





Host & Device connectors

USB 2.0

2000

1½ Mbps (Low)

12 Mbps (Full)

480 Mbps (High)



500 mA

  • Backward compatible with USB 1.1

  • Added On-the-Go (OTG)

USB 3.0

2008

1½ Mbps (Low)

12 Mbps (Full)

480 Mbps (High)

4.8 Gbps (Super)



900 mA

  • Backward USB 2.0 compatibility

  • Full-duplex

  • Power mgmt features

aSt430 USB teripheral Supports

  • USB 2.0 standard

  • Full speed USB device (12abps)

  • Device only

Note: Look at TI’s TivaC processors if you need host, device or OTG support

The MSP430’s USB port supports the USB 2.0 standard, but only operating at the Full rate. (Seeing that the fastest MSP430 devices only run up to 25MHz, it’s not hard to wonder why they cannot support the 480Mbps rate.) Additionally, since the MSP430 doesn’t provide Host support, it therefore does not provide the OTG Host/Device switching feature.

Hint:

If your product needs Host and or OTG support, you may want to check out TI’s Tiva-C line of ARM Cortex M4F processors.

Just a few years ago, in 2008, USB added the 3.0 revision. While once again backward compatible to USB 1.1 and USB 2.0, the new revision added an additional Super 4.8Gpbs rate. It also included full-duplex operation, a higher power sourcing availability of 900 mA as well as other power-management features. While this is quite advantageous for many types of endapplications – such as hard disk drives, high-end imaging systems (i.e. scanners), and such – it’s overkill for many other systems, where low power and cost are primary directives.

Bus standards, such as USB, contain a variety of layers. While these physical and data specifications are important, exploring them in great detail is outside the scope of this chapter.



AAs shown above, the USB cable provides four different signals:



  • One signal pair provides power and ground. The power signal, called VBUS, is a +5V supply. Not only does this pair provide USB 2.0 devices with up to 500 mA of power, but bringing this signal high (+5V) is how the Host begins communicating to a Device. (We’ll see more about this later in the chapter.)

  • The other pair of signals, D+ and D-, provides a differential data signal from the Host to the Device. As most hardware engineers know, using differential signaling provides more robust data transmissions.

USB 3.0 cables provide more additional signals to support its higher performance; although, that’s not something we need to deal with in this chapter.

Finally, the USB standard supports “hot swappable” devices. This means they can be connected and disconnected as needed. The USB protocol provides a means for handling this feature. To this same end, your USB application should remain flexible. By this, we mean that your application needs to be written so that it can handle an asynchronous change in the USB connection state. This might include the Host putting your Device into Suspend mode (where you receive a reduced power supply) … or the end-user disconnecting your Device from the Host by “yanking the cable”.



We’ll address many of the data/system oriented features throughout the rest of the presentation. You might note here, though, the hardware specific features. For example, “including the PHY” (physical interface) means there’s one less thing for you to put on your board. Also, the USB port has its own dedicated block of SRAM (though the system can use it when the USB port is disabled).

Also, notice the LDO voltage regulators. These let the port (and even the MSP430 device itself) operate from the +5V supply coming from an attached USB cable. Finally, the built-in PLL handles the required USB clock requirements, utilizing one of the MSP430 external clock inputs.



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