Microprocessor and Applications Model questions and Answers Module-1 3 Mark Questions



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MICROPROCESSORS AND APPLICATIONS MODEL QNS & ANS


Microprocessor and Applications

Model questions and Answers

Module-1

3 Mark Questions

  1. What is a microprocessor and what is the technology used in microprocessors?

Ans. A microprocessor may be thought of as a silicon chip around which a microcomputer is built. Microprocessor is a multipurpose, programmable, clock-driven, register based electronic device that reads binary instructions from a storage device called memory, accepts binary data as input and processes data according to those instructions, and provides as output. NMOS technology is used in microprocessors.

  1. What are the three main units of a digital computer?

Ans. The three main units of a digital computer are: the central processing unit (CPU), the memory unit and the input/output devices.

  1. What is machine language programming, assembly language programming,

Ans. Programming a computer by utilizing hex or binary code is known as machine language Programming. Programming a microcomputer by writing mnemonics is known as assembly language programming.

  1. What are meant by low level and high level languages?

Ans. Programming languages that are machine dependent are called low level languages. For example, assembly language is a low level language.

On the other hand, programming languages that are machine independent are called high level languages. Examples are BASIC, FORTRAN, C, ALGOL, COBOL, etc.



  1. What is meant by instruction and what is an instruction set?

Ans. An instruction is a command which asks the microprocessor to perform a specific task or job. The entire different instructions that a particular microprocessor can handle is called its instruction set.

  1. What an instruction consists of?

Ans. An instruction consists of an operation code (called ‘opcode’) and the address of the data

(called ‘operand’), on which the opcode operates.





  1. What is Central processing Unit ( CPU ) ? And Write the use of it.

Ans. CPU is a heart of the computer. Central processing Unit controls the operation of the computer. In a microcomputer the CPU is a microprocessor. The CPU fetches binary coded instructions from memory, decodes the instructions into a series of simple actions and carries out these actions in a sequence of steps.

  1. List the four operations commonly performed by MPU( Micro processing Unit)?

Ans.

  • Memory Read : Reads data (or instructions) from memory.

  • Memory Write: Writes Data (or instructions) into memory.

  • I/O Read: Accepts data from input devices.

  • I/O Write: Sends data to output devices

  1. What are the limitations of 8085 MPU?

Ans.

(i) The lower order address bus of the 8085 microprocessor is multiplexed (time shared) with the data bus. The buses need to be demultiplexed.

(ii) Appropriate control signals need to be generated to interface memory and I/O with the 8085.


  1. Define memory- mapped I/O.

Ans. In this method, an I/O device is treated as a memory location. The microprocessor uses 16- bit address to identify and I/O device. Thus the memory map is shared between memory and I/O devices

  1. Describe the accumulator register of 8085.

Ans. This 8-bit register is the most important one amongst all the registers of 8085. Any data input/output to/from the microprocessor takes place via the accumulator (register). It is generally used for temporary storage of data and for the placement of final result of arithmetic/logical operations. Accumulator (ACC or A) register is extensively used for arithmetic, logical, store and rotate operations.

5 Mark Questions

  1. Draw and specify the complete bit configuration of 8085 flag Register?



Ans.

S- Sign Flag . If D7 =1 , then sign flag is set, otherwise rest.

Z-Zero flag. If ALU operation results in zero, then this flag is set, Otherwise it is reset.

AC-Auxilliary flag. In an arithmetic operation ,when a carry is generated by digit D3 and passed on to digit D4, the AC flag is set. Otherwise it is reset.

P-Parity Flag. If the result of an arithmetic or logic operation has an even number of 1’s then this flag is set. Otherwise it is reset.

CY-Carry Flag. If an arithmetic operation results in a carry, the carry flag is set. Otherwise it is reset.



  1. What is the function of ALE and how does it function?

Ans. Pin 30 of 8085 is the ALE pin which stands for ‘Address Latch Enable’. ALE signal is used

to demultiplex the lower order address bus (AD0 – AD7). Pins 12 to 19 of 8085 are AD0 – AD7 which is the multiplexed address-data bus. Multiplexing is done to reduce the number of pins of 8085. Lower byte of address (A0 – A7) are available from AD0 – AD7 (pins 12 to 19) during

T1 of machine cycle. But the lower byte of address (A0 – A7), along with the upper byte A8 – A15 (pins 21 to 28) must be available during T2 and rest of the machine cycle to access memory location or I/O ports. Now ALE signal goes high at the beginning of T1 of each machine cycle and goes low at the end of T1 and remains low during the rest of the machine cycle. This high to low transition of ALE signal at the end of T1 is used to latch the lower order address byte (A0 – A7) by the latch IC 74LS373, so that the lower byte A0 – A7 is continued to be available till the end of the machine cycle.




  1. Mark Questions

1. Explain the Applications of microprocessors.

i. Microcomputers

The simplest and cheapest general purpose microprocessor -based systems are “single board microcomputers” with minimum possible hardware & software configuration.

(a)In universities and educational institutions they are used for imparting training to the students

(b)In industries, they are used for evaluation of the microprocessors or for building systems prototype systems.



ii. Liquid Crystal Display (LCD)

It is commonly used in system where low power consumption is necessary.

Examples: Watches, Calculators, Instrument panels and customer electronic displays.

LCD Display consists of crystal material is arranged in segments or in the form of a dot matrix. The crystal material can pass or block the light that passes through; thus it creates a display.



iii. Matrix Keyboard :

It is a commonly used input device when more than 8 keys are necessary. It reduces the number of interfacing devices are required. It requires 8 lines from the microprocessor to make all the connections instead of 16 lines, if the keys are connected in a linear format. When a key is pressed, it shorts one row and column. Otherwise, the row and column do not have any connection. The interfacing of a matrix keyboard requires 2 ports. (i) Output port (ii) Input port. In a matrix keyboard, the major task is to identify a key that is pressed and decode the key in terms of its binary value. This task is accomplished through either software or hardware.



iv. Domestic Appliances:

Microprocessors are also being incorporated with relatively simple domestic devices such as Ovens, Washing machines, Air conditioners, Television sets and Alarms. Microprocessor can be used in Automobiles.



v. Temperature Indicator and Controller

Microprocessors are used in typical process control applications. Microprocessor monitors a process temperature and display it on a 4 digit, seven segment display. The lower and upper limits of the temperature being monitored.



vi. Weight Cost System:

It is to provide a digital display of the weight and the price for an amount of goods. A pressure transducer is used to generate a voltage that corresponds to the weight of the goods being measured. This voltage is converted within the microprocessor into an 8421 BCD representation of the weight.



vii. Traffic Light Control:

Traffic Light Colors : Green, Yellow and Red

Microprocessors are used to give signal to traffic in traffic light controller.

viii. Instrumentation:

The processing power of the 8 bit microprocessor is more than adequate to satisfy the requirements of most of the instrumentation applications. Frequency meters, function generators, frequency synthesizers, spectrum analyzers, and many other instruments are available, where microprocessors are used as controllers.Microprocessors are also used in Medical Instrumentation. E.g. Patient Monitoring in Intensive Care Unit, Pathological Analysis and the measurement of parameters like blood pressure and temperature.



ix. Communication :

In the telephone Industry, microprocessors are used in digital telephone sets, telephone exchanges and modems. Microprocessor is used in Radio, Television and satellite communication. Microprocessors are making possible implementation of LAN and WAN for

communication of varied information through computer network.

x. Robots:

It is a Numeric controlled machine. Robots are used in the Motor Car and domestic appliance industries.



  1. With a neat diagram, explain the architecture of 8085 microprocessor. Discuss

the functions of various signals in 8085?

Ans. The 8085 is an 8-bit general-purpose microprocessor capable of addressing 64K of

memory. The diagram shows the logic pin out of the 8085 microprocessor. All the

signals can be classified into six groups: (1) address bus, (2) data bus, (3) control

and status signals, (4) power supply and frequency signals, (5) externally initiated

signals, and (6) serial I/O ports

Address Bus

The 8085 has eight signal lines, AI5-A8, which are unidirectional and used as the high-order address bus.



Multiplexed Address/Data bus

The signal lines AD7-ADo are bidirectional: they serve a dual purpose. They are used as the low-order address bus as well as the data bus. In executing an instruction, during the earlier part of the cycle, these lines are used as the low-order address bus. During the later part of the cycle, these lines are used as the data bus. (This is also known as multiplexing the bus.) However, the low-order address bus can be separated from these signals by using a latch.



Control and status signals

ALE-Address Latch Enable: This is a positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits. This signal is used primarily to latch the low-order address from the multiplexed bus and generate a separate set of eight address lines, A7-A0.

RD-Read: This is a Read control signal (active low). This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus.

WR-Write: This is a Write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location.

IO/M: This is a status signal used to differentiate between I/O and memory operations. When it is high, it indicates an I/O operation. when it is low, it indicates a memory operation. This signal is combined with RD (Read) and WR (Write) to generate I/O and memory control signals.

S1 and S0: These status signals, similar to IO/M, can identify various operations.



Power supply and Clock Frequency :

V cc: +5 V power supply.

V ss: Ground Reference.

Xl, X2: A crystal (or RC, LC network) is connected at these two pins. The frequency is internally divided by two; therefore, to operate a system at 3 MHz, the crystal should have a frequency of 6 MHz. CLK (OUT)-Clock Output: This signal can be used as the system clock for other devices.



Externally Initiated Signals including Interrupts :

INTR (input) : Interrupt Request. It is used as a general purpose interrupt.

INTA (Output) : Interrupt Acknowledge It is used to acknowledge the interrupt.

RST 7.5 (Inputs) : Restart Interrupts. These are vectored interrupts that transfer the program control to specific memory locations. They have higher priorities than the INTR interrupt. Among these three, the priority order is 7.5,6.5,5.5.

TRAP (Input) : It is nonmaskable interrupt and has the highest priority.

HOLD(Input) : It indicates that a peripheral such as a DMA (Direct memory Access) controller is requesting the use of the address and data buses.

HLDA (Output) : Hold Acknowledge .It acknowledges the HOLD request.

READY(Input) : It is used to delay the microprocessor Read or write cycles until a slow responding peripheral is ready to send or accept data.

RESET IN : When the signal on this pin goes low, the program counter is set to zero, the buses are tristated, and the MPU is reset.

RESET OUT: It indicates that the MPU is being reset.It can be used to reset other devices.



Serial I/O ports:

8085 has two signals for serial transmission : SID(Serial Input Port), SOD(Serial Output Port)



8085 Architecture

It includes the ALU (arithmetic /Logic Unit), Timing and Control Unit, Instruction Register and Decoder, Register Array, Interrupt Control, and Serial I/O Control.



ALU

The arithmetic and logic unit performs the computing functions; it includes the accumulator, the temporary register, the arithmetic and logic circuits, and five flags. The temporary register is used to hold data during an arithmetic and logic operation. The result is stored in the accumulator, and the flags are set or reset according to the result of the operation.

The flags are affected by the arithmetic and logic operations in the ALU. The flags are :

S- Sign Flag . If D7 =1 , then sign flag is set, otherwise rest.

Z-Zero flag. If ALU operation results in zero, then this flag is set, Otherwise it is reset.

AC-Auxilliary flag. In an arithmetic operation ,when a carry is generated by digit D3 and passed on to digit D4, the AC flag is set. Otherwise it is reset.

P-Parity Flag. If the result of an arithmetic or logic operation has an even number of 1’s then this flag is set. Otherwise it is reset.

CY-Carry Flag. If an arithmetic operation results in a carry, the carry flag is set. Otherwise it is reset.



Timing and Control Unit

This unit synchronizes all the microprocessor operations with the clock and generates the control signals necessary for communication between the microprocessor and peripherals.The RD and WR signals are indicating the availability of data on the data bus.



Instruction Register and Decoder.

The instruction register and the decoder are part of the ALU. When an instruction is fetched from memory, it is loaded in the instruction register. The decoder decodes the instruction and establishes the sequence of events to follow. The instruction register is not programmable and cannot be accessed through any instruction.



Register Array:

Two additional registers, called temporary registers W and Z, are included in the register array. These registers are used to hold 8-bit data during the execution of some instructions. However, because they are used internally, they are not available to the programmer.



Module-2

3 Mark Questions

  1. In how many categories the instructions of 8085 be classified?

Ans. Functionally, the instructions can be classified into five groups:

  • data transfer (copy) group

  • arithmetic group

  • logical group

  • branch group

  • stack, I/O and machine control group.

  1. What are the different types of data transfer operations possible?

Ans. The different types of data transfer operations possible are cited below:

  • Between two registers.

  • Between a register and a memory location.

  • A data byte can be transferred between a register and a memory location.

  • Between an I/O device and the accumulator.

  • Between a register pair and the stack.

  1. What is a subroutine?

Ans. A subroutine is a group of instructions, written separately from the main program, which

performs a function that is required repeatedly in the main program.



  1. Why a subroutine is used in a program?

Ans. Since a subroutine is called more than once by the main program, thus, use of subroutines

saves precious memory space. The more the number of times a subroutine is called by

the main program, the more is the saving of memory space.


  1. Give some examples of subroutines.

Ans. Some examples of subroutines called by main program are: multiplication program, time

delay subroutine, hexa-decimal converter subroutine, display subroutine, apart from any

user specific subroutines that may be needed by a programmer.

5 Mark Questions


  1. Explain in detail about the pins and signals of 8085

_ Draw the pin diagram

_ Explain each signal in detail



  1. Explain the instructions in detail about the data transfer instructions

Explain about MOV, LDA, LHLD,LXI, LDAX, STA, STAX, XCHG instructions with example

  1. Explain in detail about arithmetic instructions

Explain about ADD, ADI, SUB, SUI, SBB, SBI, DAD, DAA, INR, INX, DCR, DCX with example

  1. Explain in detail about 8085 instruction timing and execution

• Draw basic timing diagram

• Explain opcode fetch, memory read and memory write cycles with timing Diagram



  1. Give one example each of 1-byte, 2-byte and 3-byte instructions.

Ans. The examples are given below:

1-byte instruction : ADD B

2-byte instruction : MVIC, 07

3-byte instruction : LDA 4400

In 1-byte instruction, the opcode and the operand are in the same byte i.e.,


  1. Why stack is used in a program?

Ans. The stack is used to store information temporarily during the execution of a program. Also the stack is used in subroutine calls to store the return address. As an example, data generated at a certain point in a program may be needed later in the program. This data is stored in the stack and retrieved when needed. Because the number of general purpose registers (GPRs) in a microprocessor is limited–hence not all the temporary data can be stored in them and this is where the stack plays its part.

  1. What are the software instructions related to stack operations?

Ans. The following are stack related software instructions:

LXI SP, address

PUSH rp, POP rp

PUSH PSW, POP PSW

XTHL, SPHL

CALL – RET



DAD SP


  1. Mark Questions

  1. Write an assembly language program to add two 16-bit numbers.


ALGORITHM:


  1. Initialize memory pointer to data location.

  2. Get the first number from memory and store in Register pair.

  3. Get the second number in memory and add it to the Register pair.

  4. Store the sum & carry in separate memory locations.


PROGRAM:

ADDRESS

OPCODE

LABEL

MNEMONICS

OPERAND

COMMENT

8000




START

LHLD

8050H

Load the augend in DE pair through HL pair.

8001













8002













8003







XCHG




8004







LHLD

8052H

Load the addend in HL pair.

8005













8006













8007







MVI

A, 00H

Initialize reg. A for carry

8008













8009







DAD

D

Add the contents of HL

Pair with that of DE pair.



800A







JNC

LOOP

If there is no carry, go to the instruction labeled LOOP.

800B













800C













800D







INR

A

Otherwise increment reg. A

800E




LOOP

SHLD

8054H

Store the content of HL Pair in 8054H(LSB of sum)

800F













8010













8011







STA

8056H

Store the carry in 8056H through Acc.

(MSB of sum).



8012













8013













8014







HLT




Stop the program.



  1. Writ an assembly language program to find the largest element in an array.

ALGORITHM:

  1. Place all the elements of an array in the consecutive memory locations.

  2. Fetch the first element from the memory location and load it in the accumulator.

  3. Initialize a counter (register) with the total number of elements in an array.

  4. Decrement the counter by 1.

  5. Increment the memory pointer to point to the next element.

  6. Compare the accumulator content with the memory content (next element).

  7. If the accumulator content is smaller, then move the memory content.(largest element) to the accumulator. Else continue.

  8. Decrement the counter by 1.

  9. Repeat steps 5 to 8 until the counter reaches zero

  10. Store the result (accumulator content) in the specified memory location.

PROGRAM:

ADDRE

SS

OPCO

DE

LABEL

MNEM

ONICS

OPER

AND

COMMENTS

8001







LXI

H,8100

Initialize HL reg. to

8100H


8002













8003













8004







MVI

B,04

Initialize B reg with no. of comparisons(n-1)

8005













8006







MOV

A,M

Transfer first data to acc.

8007




LOOP1

INX

H

Increment HL reg. to point next memory location

8008







CMP

M

Compare M & A

8009







JNC

LOOP

If A is greater than M then go to loop

800A













800B













800C







MOV

A,M

Transfer data from M to A reg

800D




LOOP

DCR

B

Decrement B reg

800E







JNZ

LOOP1

If B is not Zero go to loop1

800F













8010













8011







STA

8105

Store the result in a memory location.

8012













8013













8014







HLT




Stop the program

Module-3

3 Mark Questions

  1. Write about RST pins in 8085?

Ans. In 8085 ,three RST pins are available, such as RST 7.5 ,RST 6.5 , RST 5.5. RST represents Restart Interrupts. These are vectored interrupts that transfer the program control to specific memory locations. They have higher priorities than the INTR interrupt. Among these three, the priority order is 7.5,6.5,5.5.

  1. Mention the interrupt pins of 8085.

Ans. There are five (5) interrupt pins of 8085—from pin 6 to pin 10. They represent TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR interrupts respectively. These five interrupts are ‘hardware’ interrupts.

  1. Explain maskable and non-maskable interrupts.

Ans. An interrupt which can be disabled by software means, is called a maskable interrupt. Thus an interrupt which cannot be masked is an unmaskable interrupt.

  1. Which is the non-maskable interrupt for 8085?

Ans. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an interrupt comes via TRAP, 8085 will have to recognise the interrupt.

  1. Do the interrupts of 8085 have priority?

Ans. Yes, the interrupts of 8085 have their priorities fixed—TRAP interrupt has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and lastly INTR.

  1. What is meant by priority of interrupts?

Ans. It means that if 8085 is interrupted by more than one interrupt at the same time, the one which is having highest priority will be serviced first, followed by the one(s) which is (are) having just next priority and so on.

For example, if 8085 is interrupted by RST 7.5, INTR and RST 5.5 at the same time, then the sequence in which the interrupts are going to be serviced are as follows: RST 7.5, RST 5.5 and INTR respectively.



5 Mark Questions

  1. In what way INTR is different from the other four hardware interrupts?

Ans. There are two differences, which are discussed below:

(1). While INTR is not a vectored interrupt, the other four, viz., TRAP, RST 7.5, RST 6.5 and RST 5.5 are all vectored interrupts. Thus whenever an interrupt comes via any one of these four interrupts, the internal control circuit of 8085 produces a CALL to a predetermined vector location. At these vector locations the subroutines are written. On the other hand, INTR receives the address of the subroutine from the external device itself.

(2). Whenever an interrupt occurs via TRAP, RST 7.5, RST 6.5 or RST 5.5, the corresponding returns address (existing in program counter) is auto-saved in STACK, but this is not so in case of INTR interrupt.


  1. Discuss the INTR interrupt of 8085.

Ans. The following are the characteristics of INTR interrupt of 8085:

  • It is a maskable interrupt

  • It has lowest priority

  • It is a non-vectored interrupt.

Sequentially, the following occurs when INTR signal goes high:

1. 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal remains high till the completion of an instruction, then 8085 sends æææææ

out an active low interrupt acknowledge (INTA) signal. æææææ

3. When INTA signal goes low, external logic places an instruction OPCODE on the data bus.

4. On receiving the instruction, 8085 saves the address of next instruction (which would have otherwise been executed) in the STACK and starts executing the ISS (interrupt service subroutine).



  1. Draw the SIM instruction format and discuss.

Ans. D7 and D6 bits are utilised for serial outputting of data from accumulator. D5 bit is a don’t care bit, while bits D4–D0 are used for interrupt control. D4 bit can clear the D F/F associated with RST 7.5. D3 bit is mask set enable (MSE) bit, while bits D2–D0 are the masking bits corresponding to RST 7.5, RST 6.5 and RST 5.5 respectively. None of the flags are affected by SIM instruction. By employing SIM instruction, the three interrupts RST 7.5, RST 6.5 and RST 5.5 can be masked or unmasked. For masking any one of these three interrupts, MSE (i.e., bit D3) bit must be 1.



  1. Show the RIM instruction format and discuss the same.

Ans. RIM stands for ‘Read interrupt mask’ and its format is as follows:



12 Mark Questions

  1. Draw the interrupt circuit diagram for 8085 and explain.

Ans. Figure 4.6 is the interrupt circuit diagram of 8085. It shows the five hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR along with the software interrupts RST n: n = 0 to 7. Trap is both edge and level sensitive interrupt. A short pulse should be applied at the trap input, but the pulse width must be greater than a normal noise pulse width and also long enough for the μP to complete its current instruction. The trap input must come down to low level for it to be recognised for the second time by the system. It is having highest priority.

Next highest priority interrupt is RST 7.5 which responds to the positive edge (low to high transition) of a pulse. Like trap, it also has a D F/F whose output becomes 1 on accepting the RST 7.5 input, but final call to vector location 3C00H is reached only if RST 7.5 remains unmasked and the program has an EI instruction inserted already. These are evident from the circuit. If R 7.5 (bit D4 of SIM instruction) is 1, then RST 7.5 instruction will be overlooked i.e., it can override any RST 7.5 interrupt. Like RST 7.5, final call locations 3400H and 2C00H corresponding to interrupts at RST 6.5 and RST 5.5 are reached only if the two interrupts remain unmasked and the software instruction EI is inserted.

The three interrupts RST 7.5, RST 6.5 and RST 5.5 are disabled once the system accepts an interrupt input via any one of these pins—this is because of the generation of ‘any interrupt acknowledge’ signal which disables them. Any of the software RST instructions (RST n : n = 0 to 7) can be utilised by using INTR instruction and hardware logic. RST instructions are utilised in breakpoint service routine to check register(s) or memory contents at any point in the program.



Module-4


  1. Mark Questions

  1. List the major sections of the 8279 keyboard/display interface

Ans.

i) Keyboard section

ii) Scan Section

iii) Display section

iv) CPU interface section


  1. How many hardware interrupts 8085 supports?

Ans. It supports five (5) hardware interrupts—TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

  1. How many ports are there in 8255 and what are they?

Ans. Basically there are three ports in 8255, viz., Port A, Port B and Port C, each having 8 pins. Again Port C can be divided into Ports Cupper and Port Clower—each having four pins i.e., a nibble. Thus 8255 can be viewed to have four ports—Port A, Port B, Port Cupper and Port Clower.

  1. What is BSR mode and what are its characteristics?

Ans. BSR mode stands for Bit Set Reset mode.

The characteristics of BSR mode are:



  • BSR mode is selected only when D7 = 0 of the Control Word Register (CWR).

  • Concerned with bits of port C.

  • Individual bits of Port C can either be Set or Reset.

  • At a time, only a single bit of port C can be Set or Reset.

  • Is used for control or on/off switch.

  • BSR control word doesn’t affect ports A and B functioning.

  1. Describe the Scanned Sensor Matrix Mode.

Ans. In the Scanned Sensor Matrix Mode of operation, the keys are arranged in the form of a matrix, with the scan lines (SL0 – SL2) forming the columns and return lines (RL0 – RL7) forming the rows. The open/closed condition of the key is stored in a RAM location. The size of the matrix be 8 × 8 or 4 × 8 for encoded and decoded scan lines respectively.

The data entering via the RL lines are admitted into eight columns of the sensor RAM—thus each RAM position corresponds to a specific switch position. Apart from switches, other logic circuit output lines can be connected to the RL lines.



  1. Describe the Strobed Input Mode.

Ans. In this mode, data are placed on the return lines (RLs). The source of data may be an encoded keyboard or a switch matrix. The data so entering go to FIFO RAM and are accepted on the rising edge of a CNTL/STB pulse.

  1. What are the different functional blocks in 8259?

Ans. PIC 8259 has four different functional blocks viz.,

(i) Interrupt and Control logic block

(ii) Data bus buffer

(iii) Read/Write control logic block and

(iv) Cascade buffer/comparator section.

5 Mark Questions


  1. Distinguish between the three modes of 8255.

Ans. The three modes are Mode 0, Mode 1 and Mode 2. These are I/O operations and selected only if D7 bit of the control word register is put as 1.

The three operating modes of 8255 are distinguished in the following manner:



Mode 0: This is a basic or simple input/output mode, whose features are:

  • Outputs are latched.

  • Inputs are not latched.

  • All ports (A, B, CU, CL) can be programmed in either input or output mode.

  • Ports don’t have handshake or interrupt capability.

  • Sixteen possible input/output configurations are possible.

Mode 1: In this mode, input or outputting of data is carried out by taking the help of handshaking signals, also known as strobe signals. The basic features of this mode are:

  • Ports A and B can function as 8-bit I/O ports, taking the help of pins of Port C.

  • I/Ps and I/Ps are latched.

  • Interrupt logic is supported.

  • Handshake signals are exchanged between CPU and peripheral prior to data transfer.

  • In this mode, Port C is called status port.

There are two groups in this mode—group A and group B. They can be configured separately. Each group consists of an 8-bit port and a 4-bit port. This 4-bit port is used for handshaking in each group.

Mode 2: In this mode, Port A can be set up for bidirectional data transfer using handshake signals from Port C. Port B can be set up either in mode 0 or mode 1.

  1. Write down the main features of 8259.

Ans. The main features of 8259 are as follows:

1. A single 8259 can handle 8 vectored priority interrupts.

2. 9 numbers of 8259 can be cascaded to have 64 levels of vectored priority interrupts in a mC system.

3. The priority modes can be changed or reconfigured dynamically at any time during the main program.

4. It can be operated in various interrupt modes—fully nested, rotating priority, special mask and polled.

5. 8259 can be used with either 8080/8085 or 8086/8088 microprocessor.

6. 8259 supports both edge and level triggered mode of interrupts.

7. The CALL address can be programmed to have a spacing of either 4 or 8 memory locations.

8. The data bus is buffered.

9. The AEOI (Automatic End Of Interrupt) can be programmed.



  1. Describe the EOI command.

Ans. This command stands for End of Interrupt (EOI l.

The interrupt service bit (that is being currently serviced) can be reset by an End of Interrupt Command. This is issued by the CPU, usually just before coming out of the interrupt service routine.



  1. Draw the pin diagram and functional block diagram of 8254.

Ans. The pin diagram and functional block diagram of 8254 are shown below:



12 Mark Questions

  1. Draw and discuss about the internal architecture and signals of the Keyboard/Display Controller 8279.

The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed display.Tha disadvantage of the software approach is that the microprocessor is occupied for a considerable amount of time in checking the keyboard and refreshing the display.The 8279 relieves the processor from these two tasks.The disadvantage of using the 8279 is the cost.

The 8279 is a 40-pin device with two major segments;Keyboard and Display.The keyboard segment can be connected to a 64-contact key matrix.Keyboard entries are debounced and stored in the internal FIFO memory;an interrupt signal is generated with each entry.The display segment can provide a 16-charactor scanned display interface with such devices as LEDs.



Block Diagram of 8279:

The block diagram consists of four major sections.(i) Keyboard Section (ii) Display Section (iii) Scan Section (iv) Processor Interface Section.







  1. Keyboard Section:

This section has eight lines of RL0-RL7 that can be connected to a 8 columns of a keyboard section and two additional lines for SHIFT and CNTL/STB(Control/Strobe).The keys are automatically debounced and the keyboard can operate in two modes Two-Key lockout or N-Key rollover.In the two key lockout mode,if the two keys are pressed almost simultaneously,only the first key is recognised.In the N-Key rollover mode,simultaneous keys are recognised and thier codes are stored in the internal buffer;it can also be setup sothat no key is recognised until only one key remains pressed.

The keyboard section also includes 8x8 FIFO(First In First Out) RAM.The FIFO RAM consists of eight registers that can store eight keyboard entries;each is then read in the order of entries.The status logic keeps the track of the number of entries and provides an IRQ (interrupt Request) signal when the FIFO is not empty.



(ii) Display Section:

The display section has eight output lines devided in to two groups,Ao-A3 and Bo-B3 .These lines can be used, either as a group of eight lines or as two groups of four,in conjunction with the scan lines for a multiplexed display.The display can be blanked by using BD line.This section includes 16x8 display RAM.The microprocessr can read from or write in to any of these registers.



(iii) Scan Section:

The scan section has a scan counter and four scan lines (SL0-SL3).These four scan lines can be decoded using a 4-to-16 decoder to generate 16 lines for scanning.These scan lines can be connected to the rows of a matrix keyboard and digit drivers of a multiplexed display.



(iv) Processor Interface Section:

This section includes eight bidirectional data lines (DB0-DB7) ,one interrupt request line(IRQ) and six lines for interfacing including the buffer address line A0.

When A0 is high ,signals are interpreted as control words or status;when A0 is low,signals are interprted as data.The IRQ lines goes high whenever the data entriesare stored in the FIFO.This signal is used to interrupt the microprocessor to indicate the availability of data.


  1. Draw and explain the internal block diagram of programmable peripheral interface 8255A.

  2. Draw and explain the block diagram of DMA Controller 8237.

  3. Draw and explain the internal block diagram of programmable interval timer 8254.

Module-5

3 Mark Questions


  1. What are the main features of Intel 8086:

  • Introduced in 1978, the 8086 was the first 80X86 family and is the basis for all Intel microprocessors that followed.

  • The 8086 was a 16-bit microprocessor (16-bit data bus) and represented a significant departure from the earlier 8-bit devices.

  • Owned 20 address lines (allowing 220 memory locations to be accessed).

  • It is available as 40-pin Dual-Inline-Package (DIP).

  • The various versions of the 8086 operated at clock frequencies of 5,8, or 10MHz.




  1. Different types of interrupts that 8086 can implement.

8086 μP can implement seven different types of interrupts.



  • NMI and INTR are external interrupts implemented via Hardware.(User defined hardware interrupts)

  • INT n, INTO and INT3 (breakpoint instruction) are software interrupts implemented through Program.(User defined software interrupts)

  • The ‘divide-by-0’ and ‘Single-step’ are interrupts initiated by CPU.(Predefined interrupts)

  1. List the functions of Bus Interface Unit in 8086.

• Sends out addresses

• Fetches instructions from memory

• Reads data from ports and memory

• Writes data to port and memory



  1. Write any two advantages of segment registers in 8086

a). It allows the memory capacity to be 1MB even though the address associated with individual instructions are 16 bits wide.

b). It allows the instruction,data, or stack portion of a program to be more than 64KB long by using more than one code, data, or stack segment




  1. What is the use of Instruction pointer in 8086 ?

Instruction pointer holds the 16 bit address of the next code byte within the code segment. The value contained in the IP is called effective address or offset. It contains the distance from the base address to the next instruction byte to be fetched.


  1. Write about the auxiliary carry flag used in 8086 ?

It is set if there is a carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction. This flag is used exclusively for BCD arithmetic.


  1. When the Overflow flag is set ?

For addition of 16 bits, this flag is set when there is a carry into the MSB and no carry out of the MSB.

5 Mark Questions

  1. Describe the status register of 8086.

Out of nine flags, six are condition flags and three are control flags. The control flags are TF (Trap), IF (Interrupt) and DF (Direction) flags, which can be set/reset by the programmer, while the condition flags [OF (Overflow), SF (Sign), ZF (Zero), AF (Auxiliary Carry), PF (Parity) and CF (Carry)] are set/reset depending on the results of some arithmetic or logical operations during program execution.

CF is set if there is a carry out of the MSB position resulting from an addition operation or if a borrow is needed out of the MSB position during subtraction.

PF is set if the lower 8-bits of the result of an operation contains an even number of 1’s. AF is set if there is a carry out of bit 3 resulting from an addition operation or a borrow required from bit 4 into bit 3 during subtraction operation.

ZF is set if the result of an arithmetic or logical operation is zero.

SF is set if the MSB of the result of an operation is 1. SF is used with unsigned numbers.

OF is used only for signed arithmetic operation and is set if the result is too large to be fitted in the number of bits available to accommodate it


  1. What are the advantages of memory segmentation in8086?

Ans. Memory segmentation, as implemented for 8086, gives rise to the following advantages:

  • Although the address bus is 20-bits in width, memory segmentation allows one to work with registers having width 16-bits only.

  • It allows instruction code, data, stack and portion of program to be more than 64 KB long by using more than one code, data, extra segment and stack segment.

  • In a time-shared multitasking environment when the program moves over from one user’s program to another, the CPU will simply have to reload the four segment registers with the segment starting addresses assigned to the current user’s program.

  • User’s program (code) and data can be stored separately.

  • Because the logical address range is from 0000 H to FFFF H, the same can be loaded at any place in the memory.

  1. Discuss logical address, base segment address and physical address.

Ans. The logical address, also goes by the name of effective address or offset address (also known as offset), is contained in the 16-bit IP, BP, SP, BX, SI or DI. The 16-bit content of one of the four segment registers (CS, DS, ES, SS) is known as the base segment address. Offset and base segment addresses are combined to form a 20-bit physical address (also called real address) that is used to access the memory. This 20-bit physical address is put on the address bus (AD19 – AD0) by the BIU.

  1. Describe how the 20-bit physical address is generated.

Ans. The 20-bit physical (real) address is generated by combining the offset (residing in IP, BP, SP, BX, SI or DI) and the content of one of the segment registers CS, DS, ES or SS. The process of combination is as follows: The content of the segment register is internally appended with 0 H (0000 H) on its right most end to form a 20-bit memory address—this 20-bit address points to the start of the segment. The offset is then added to the above to get the physical address.

Fig. 12.3 shows pictorially the actual process of generating a 20-bit physical address.







  1. Describe how memory is organised for 8086 μP?

Ans. The total address space 1 MB of 8086 is divided into 2 banks of memory—each bank of maximum size 512 KB. One is called the high order memory bank (or high bank) and the other low order memory bank (or low bank).

Low bank, high bank or both banks can be accessed by utilizing two signals BHE and A0. Table 12.1 shows the three possible references to memory. The high bank is selected for A0=1 and BHE=0 and is connected to D15–D8 while the low bank is selected for A0=0 and BHE =1. Neither low bank nor high bank would selected for A0=1 and BHE =1.

Fig. 12.4 shows how the total address space (1MB) of 8086 is physically implemented by segregating it into low and high banks. It also shows that CS signal of the high bank is connected to BHE while the CS signal of the low bank is connected to A0.



12 Mark Questions


  1. Explain the architecture of 8086 microprocessor

• Features of 8086

• Draw the architecture

• Explanation


  1. Explain the minimum mode operation of 8086 in detail.

• When 8086 is in minimum mode

• Pin definitions for the minimum mode

• Diagrams used for minimum mode system

• Explanations

• Timing diagram


  1. Explain the maximum mode operation of 8086 in detail.

• When 8086 is in maximum mode

• Pin definitions for the maximum mode

• Diagrams used for maximum mode system

• Explanations



• Timing diagram

  1. Draw the Read and Write bus cycles for 8086 μP in Minimum mode.

Ans. Fig. 12.7 shows the Read and Write bus cycles for 8086 μP in the Minimum mode. The bus cycle consists of 4T states. ALE signal stays high for T1 state at the end of which it goes low which is utilised by latches to latch the address. Hence, during T2 – T4 states, AD15 – AD0 lines act as data lines. The M/ IO , RD and WR signals can be combined to generate individual IOR, IOW and MEMR, MEMWsignals. The Read and Write cycles show that data are made available during T3 and T2 states respectively.



MUHAMMED RIYAS A.M, ASST. PROFESSOR, ECE DEPT, MCET PATHANAMTHITTA


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