Microprocessor Simulator 0 Help

Binary and Hexadecimal

• Converting Between Binary and Hex

The CPU works using binary. Electronically this is done with electronic switches that are either on or off. This is represented on paper by noughts and ones. A single BIT or binary digit requires one wire or switch within the CPU. Usually data is handled in BYTES or multiples of bytes. A Byte is a group of eight bits. A byte looks like this

1. 01001011

1. 0100    1011

1.  BINARY  HEXADECIMAL  DECIMAL 0 0 0 0000 0 0 1110 0 1 0220 0 1 1330 1 0 0440 1 0 1550 1 1 0660 1 1 1771 0 0 0881 0 0 1991 0 1 0A101 0 1 1B111 1 0 0C121 1 0 1D131 1 1 0E141 1 1 1F15 

2. EXAMPLE

Using the table above

The answer ...

To convert the other way take a hexadecimal such as E7.

Look up E in the table. It is 1110.

• Instruction Set Summary

AL, BL, CL and DL are eight bit, general purpose registers where data is stored.

Square brackets indicate RAM locations. For example [15] means RAM location 15.

Data can be moved from a register into into RAM and also from RAM into a register.

Registers can be used as pointers to RAM. [BL] is the RAM location that BL points to.

All numbers are in base 16 (Hexadecimal).

1. 
   Move Instructions. Flags NOT set. Assembler  Machine Code     Explanation MOVAL,15     D0 00 15AL = 15    Copy 15 into AL MOVBL,[15] D1 01 15BL = [15] Copy RAM[15] into AL MOV[15],CL D2 15 02[15] = CL Copy CL into RAM[15]  MOVDL,[AL] D3 03 00DL = [AL] Copy RAM[AL] into DL MOV[CL],AL D4 02 00[CL] = AL Copy AL into RAM[CL] 
   

1. 
   Direct Arithmetic and Logic. Flags are set. Assembler  Machine Code       ADDAL,BL     A0 00 01AL = AL + BL   SUBBL,CL A1 01 02BL = BL - CL   MULCL,DL A2 02 03CL = CL * DL   DIVDL,AL A3 03 00DL = DL / AL   INCDL A4 03DL = DL + 1   DECAL A5 00AL = AL - 1   ANDAL,BL AA 00 01AL = AL AND BL    ORCL,BL AB 03 02CL = CL OR BL   XORAL,BL AC 00 01AL = AL XOR BL   NOTBL AD 01BL = NOT BL   ROLAL 9A 00Rotate bits left. LSB = MSB RORBL 9B 01Rotate bits right. MSB = LSB SHLCL 9C 02Shift bits left. Discard MSB.  SHRDL 9D 03Shift bits right. Discaed LSB.
   

1. 
   Immediate Arithmetic and Logic. Flags are set. Assembler  Machine Code       ADDAL,12 B0 00 12AL = AL + 12   SUBBL,15 B1 01 15BL = BL - 15   MULCL,03 B2 02 03CL = CL * 3   DIVDL,02 B6 03 02DL = DL / 2   ANDAL,10 BA 00 10AL = AL AND 10   ORCL,F0 BB 02 F0CL = CL OR F0   XORAL,AA BC 00 AAAL = AL XOR AA   
   

1. 
   Compare Instructions. Flags are set. Assembler  Machine Code Explanation CMPAL,BL DA 00 01Set 'Z' flag if AL = BL.
   Set 'S' flag if AL < BL.
      CMPBL,13 DB 01 13Set 'Z' flag if BL = 13.
   Set 'S' flag if BL < 13.
      CMPCL,[20]  DC 02 20Set 'Z' flag if CL = [20].
   Set 'S' flag if CL < [20].
    
   

1. 
   Branch Instructions. Flags NOT set. Depending on the type of jump, different machine codes can be generated.
   Jump instructions cause the instruction pointer (IP) to be altered. The largest
   possible jumps are +127 bytes and -128 bytes.
   

1. 
   Procedures and Interrupts. Flags NOT set. CALL, RET, INT and IRET are available only in the registered version. Assembler  Machine Code Explanation CALL30 CA 30Save IP on the stack and jump to the
   procedure at address 30. RET  CBRestore IP from the stack and jump to it. INT02 CC 02Save IP on the stack and jump to the address
   (interrupt vector) retrieved from RAM[02]. IRET  CDRestore IP from the stack and jump to it.
   

1. 
   Stack Manipulation Instructions. Flags NOT set. Assembler  Machine Code Explanation PUSHBL E0 01BL is saved onto the stack. POPCL E1 02CL is restored from the stack. PUSHF  EASR flags are saved onto the stack. POPF  EBSR flags are restored from the stack.
   

1. 
   Input Output Instructions. Flags NOT set. Assembler  Machine Code Explanation IN07 F0 07Data input from I/O port 07 to AL. OUT01 F1 01Data output to I/O port 07 from AL.
   

1. 
   Miscellaneous Instructions. CLI and STI set I flag.  Assembler  Machine Code Explanation CLO  FEClose visible peripheral windows. HALT  00Halt the processor. NOP  FFDo nothing for one clock cycle. STI  FCSet the interrupt flag in the Status Register. CLI  FDClear the interrupt flag in the Status Register. ORG40 Code originAssembler directive: Generate code starting
   from address 40. DB"Hello" Define byteAssembler directive: Store the ASCII codes
   of 'Hello' into RAM. DB84 Define byteAssembler directive: Store 84 into RAM.
   

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