Pwnos design Document Version 0a



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Document Scope


The objective of this document is to provide thorough details of the design of PwnOS, up to but not including the level of exhaustive function lists. Some details given in this document might be considered more implementation than design, but the intent is to have more emphasis on details that are less likely to change than details that are more likely to change. For documentation relating to implementation details, please see (1).
This document does not provide introductory, tutorial, or reference documentation on hardware devices, protocols, data structures, standards, or computer languages, except if and when useful in describing their relation to the design of PwnOS. For details on these, please see the cited material.

Abbreviations





Abbreviation

Term

ACPI

Advanced Configuration and Power Interface

API

Application Programming Interface

APIC

Advanced Programmable Interrupt Controller

ATA

AT Attachment

AVL Tree

Adelson-Velsky Landis Tree

BIOS

Basic Input/Output System

CPU

Central Processing Unit

DMA

Direct Memory Access

FTP

File Transfer Protocol

GB

GigaBytes (230 bytes in this document)

GDT

Global Descriptor Table

HP

Hewlett-Packard Company

HPC

High-Performance Computing

HTTP

HyperText Transfer Protocol

IBM

International Business Machines Corporation

I/O

Input / Output

IP

Internet Protocol

IPC

Inter-Process Communication

ITRON

Industrial The Real-time Operating system Nucleus

LAPIC

Local APIC

LSI

Large Scale Integration (of circuitry)

MB

MegaBytes (220 bytes in this document)

MBR

Master Boot Record (sector 0)

MFT

Master File Table

NTFS

New Technology File System

OS

Operating System

PCI

Peripheral Component Interconnect

PDs

Page Directories

PDPT

Page Directory Pointer Table

PIT

Programmable Interval Timer

PL0

Privilege Level 0 (supervisor privilege)

PL3

Privilege Level 3 (user privilege)

PML4

Page Map Level 4 table

PS/2

Personal System/2 (or the ports thereof)

PTs

Page Tables (or in general the page mapping)

RAM

Random-Access Memory

RPTs

Reverse Page Tables (not standardised)

SGI

Silicon Graphics Incorporated

SIMD

Single-Instruction, Multiple-Data

SSE#

Streaming SIMD Extensions # (e.g. SSE3)

TB

TeraBytes (240 bytes in this document)

TCP

Transmission Control Protocol

TLB

Translation Lookaside Buffer

TSS

Task State Segment

UDP

User Datagram Protocol

USB

Universal Serial Bus

VBE

VESA BIOS Extensions





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