Report itu-r m. 2038 Technology trends
GKOS implementation examples
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- 1 Background
- 2 Processor architecture
4.3 GKOS implementation examplesThe dimensions of the GKOS keyboard depend on the form, size and weight of the terminal. In any case, there are six keys on the back of the equipment: three for the left and three for the right hand. Pinky fingers are used only for balancing the grip of the terminal and thumbs are kept on the sides of the front panel to manage the pointing device. 
The left thumb can operate keys corresponding the left and right mouse switch (the upper “select” key and the lower “menu” key), and the right thumb then moves the pointer. This way both the mouse and keyboard functions can be fully controlled, having the fingers at the same position all the time. The virtual keyboard at the lower part of the display can be hidden after getting accustomed to the method. The tiny mobile device below has a foldable GKOS keypad that can be used while holding the terminal or also when it is standing on a desk top (the keyboard folded out and the display facing the user).   
Annex 14 Reconfigurable processors 1 BackgroundIn recent years, new-type embedded processors have been developed. The outstanding feature of these processors is that their performance is not improved simply by increasing the clock speed or the memory bandwidth, but by providing an ability to implement a custom pipeline that allows custom instructions to be defined and executed based on what is required for the application. There are two types of approach to realize user custom instructions. One is configurable processor and another is reconfigurable processor. Configurable processors are promising in achieving great performance advance because they allow the creation of custom instructions and their execution units optimized for each application. However, configurable processors cannot be added new custom instructions after fabrication. In wireless communication systems, system specifications are often changed or they are slightly different from country to country. Therefore, processors that can realize variety kinds of instructions and can be added new custom instructions after fabrication are required to adapt those situations. The latter approach fits this requirement. These processors include arrays of arithmetic-and-logic units (ALUs) and other operational units. These processors allow the connection configuration of the execution units to be changed to match the data processing flow required for the application. The amount of configuration information required is low because, unlike field programmable gate arrays (FPGAs), the granularity of the circuit included in the processor is not small. This means that it is possible to provide multiple sets of on-chip configuration information and dynamically select one of these sets at individual clock cycles. These reconfigurable processors would be extremely fast if processing sequences could be mapped to the execution unit array. The example shown in this Annex is an embedded processor which is based on the VLIW architecture [Suga et al., 2000; Okano et al., 2002]. This processor is designed for media applications and include an implementation of single instruction multiple data (SIMD) type media operation instructions. Therefore, they can perform fast media processing. The reconfigurable execution unit is developed so that general-purpose processor core can handle user defined custom instructions. The reconfigurable unit is not an ALU array type. By focusing to bit level data processing, it enables the processor to achieve higher performance with small area overhead. The rest of this Annex reports the characteristics, functions, performance, and other nature of the reconfigurable unit designed for general-purpose processor as an example of reconfigurable processor. 2 Processor architecture2.1 Overall structureFigure 38 shows an example of reconfigurable processor that includes the reconfigurable unit (R unit). The integer unit (I-unit) consists of an instruction fetch block, various controllers, an integer register file (GR: 32 bits × 32 words), and two integer pipelines. The media unit (M-unit) consists of a media register file (FR: 32 bits × 32 words) and two media pipelines. The cache unit (S-unit) includes a two-way set-associative combination of two 8 K cache memories one for instructions and the other for data. 
R-unit is composed of an execution pipeline (R-pipe), which can dynamically change the internal configuration based on configuration information signals and configuration memory, which holds configuration information. One configuration within R-pipe is defined by 256 bits of information. Configuration memory is a 1 K RAM with 32 entries. It can hold configuration information represented by 32 types of custom instructions. Data in the configuration memory can be rewritten by using a configuration load instruction. This allows over 32 custom instructions to be defined and executed. This type of general-purpose processor includes a powerful instruction set for media operation. Therefore, custom instruction processing performed within R-unit is not intended to further increase the media processing speed, but to improve the efficiency of processing at which this type of general-purpose processor is weak. More specifically, this type of general-purpose processor is efficient in word-level data processing, but is weak at bit-level data processing, such as encryption-related processing. R-unit is designed to perform bit-level data more efficiently. Directory: dms pub -> itu-r -> opb -> rep rep -> Report itu-r m. 2243 (11/2011) rep -> Report itu-r bt. 2053-2 (11/2009) L rep -> Report itu-r sa. 2312-0 (09/2014) rep -> Report itu-r rep -> Report itu-r sm. 2179 (09/2010) Short-range radiocommunication devices measurements rep -> Report itu-r rep -> Report itu-r rs. 2194 (10/2010) rep -> Report itu-r rs. 2165 (09/2009) rep -> Rep. Itu-r bs. 2104 Download 490.99 Kb. Share with your friends:
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