Jaume Abella, Ramon Canal, Antonio Gonzales, “Power and Complexity-Aware Issue Queue Designs”, IEEE Micro, Vol. 23, No. 5, Sept. 2003.
Y. Almog R. Rosner N. Schwartz, A. Schmorak. “Specialized Dynamic Optimizations for High Performance Energy-Efficient Microarchitecture”, Proceedings of the 2nd International Symposium on Code Generation and Optimization, Mar. 2004.
Erik R. Altman, et al. “BOA: the Architecture of a Binary Translation Processor”, IBM Research Report RC 21665, Dec 2000.
Erik R. Altman, Kemal Ebcioglu, Michael Gschwind and Sumedh Sathaye, “Advances and Future Challenges in Binary Translation and Optimization”, Proceedings Of the IEEE, Special Issue on Microprocessor Architecture and Compiler Technology, Nov. 2001, pp. 1710-1722.
Erik R. Altman, David Kaeli, and Yaron Sheffer, “Welcome to the opportunities of Binary translation”, IEEE Computer 33(3), Mar. 2000.
AMD Corp., “AMD x86-64 Architecture Programmer’s Manual, vol. 5: 64-bit Media and x87 Floating-Point Instrutions”, AMD Corp., 2005
Matthew Arnold, Stephen Fink, David Grove, Michael Hind, Peter F. Sweeney, “Adaptive Optimization in the Jalapeno JVM”, Proceedings of the ACM SIGPALN Conference on Object-Oriented Programming systems, Languages, and Applications, pp. 47-65, Oct 2000.
James E. Bahr, et al. “Architecture, Design, and Performance of Application Systems/400 (AS/400) Multiprocessors”, IBM Journal of Research and Development, vol. 36, No. 1, pp. 12-23, Jan. 1990.
Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia, “Dynamo: A Transparent Dynamic Optimization System”, Proceedings of International Symposium on Programming Language Design and Implementation, pp. 1-12, Jun. 2000.
Thomas Ball, James R. Larus. “Efficient Path Profiling”. Proceedings of the 29thInternational Symposium on Microarchitecture, pages 46-57, 1996.
Leonid Baraz, et al. “IA-32 Execution Layer: a two phase dynamic translator designed to support IA-32 applications on Itaniumâ-based systems” Proceedings of the 36th International Symposium on Microarchitecture pp. 191-202 Dec. 2003.
Michael Bekerman, et al., “Early Load Address Resolution via Register Tracking”, Proceedings of the 27th International Symposium of Computer Architecture, pp. 306-315, May 2000.
V. Bertsis, “Security and Protection of Data in the IBM System/38”, Proceedings of the 7thInternational Symposium on Computer Architecture, June. 1980, pp. 245-252
Michael D. Bond, Kathryn S. McKinley, “Practical Path Profiling for Dynamic Optimizers”, Proceedings of the 3rd International Symposium on Code Generation and Optimizations, pp. 205-216, Mar. 2005.
P. Bonseigneur, "Description of the 7600 Computer System", Computer Group News, May 1969, pp. 11-15.
Anne Bracy, Prashant Prahlad, Amir Roth, “Dataflow Mini-Graph: Amplifying Superscalar Capacity and Bandwidth”, Proceedings of the 37th International Symposium on Micro architecture, Dec. 2004.
Mary D. Brown, Jared Stark, and Yale N. Patt, “Select-Free Instruction Scheduling Logic”, Proceedings of the 34th International Symposium on Microarchitecture, pp. 204-213, Dec. 2001.
Derek Bruening, Timothy Garnett, Saman Amarasinghe, “An Infrastructure for Adaptive Dynamic Optimization”, Proceedings of the 1st International Symposium on Code Generation and Optimization, pp. 265-275, Mar. 2003.
D. Burger, T. M. Austin, and S. Bennett, “Evaluating Future Microprocessors: The SimpleScalar ToolSet”, University of Wisconsin – Madison, Computer Sciences Department, Technical Report CS-TR-1308, 1996.
Anton Chernoff, Mark Herdeg, Ray Hookway, et al, “FX!32: A Profiler-Directed Binary Translator”, IEEE Micro (18), March/April 1998.
Yuan Chou, John P. Shen, “Instruction Path Coprocessors”, Proceedings of the 27th International Symposium on Computer Architecture, Jun. 2000.
Yuan Chou, Pazheni Pillai, Herman Schmit, John P. Shen, “PipeRench Implementation of the Instruction Path Coprocessor”, Proceedings of the 33rd International Symposium on Microarchitecture pp. 147-258 Dec. 2000
Nathan Clark, et al, “Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization”, Proceedings of the 37th International Symposium on Microarchitecture, Dec. 2004.
Robert F. Cmelik, David R. Ditzel, Edmond J. Kelly, Colin B. Hunter, et al, “Combining Hardware and Software to Provide an Improved Microprocessor”, US Patent 6,031,992, Feb. 2000.
Robert F. Cmelik, David Keppel, “Shade: A Fast Instruction-Set Simulator for Execution Profiling”, Technical Report UWCSE 93-06-06, University of Washington, Jun. 1996.
Robert Cohn, P. Geoffrey Lowney, “Hot Cold Optimization of Large Windows/NT Applications”, Proceedings of the 29th International Symposium on Microarchitecture, pp. 80-89 Dec. 1996.
T. M. Conte, K. N. Menezes, M. A. Hirsch, “Accurate and Practical Profile-Driven Compilation Using the Profile Buffer”, Proceedings of the 23rd International Symposium on Computer Architecture, 1996