aiT is the leading tool for computing worst case execution times (WCETs).
A prototype implementation of the UCB computation as developed by Saarland University has been integrated by AbsInt into the aiT Timing Analyzer. The analysis is implemented for the ARM7 and has been tested on smaller benchmark programs.
Current work is concerned with optimising the performance of the analysis and exploring its potential on larger examples. Implementations for other processors are also underway.
Daniel Grund, Jan Reineke, Reinhard Wilhelm: A Template for Predictability Definitions with Supporting Evidence. PPES 2011: 22-31
Daniel Grund, Jan Reineke, Gernot Gebhard: Branch target buffers: WCET analysis framework and timing predictability. Journal of Systems Architecture - Embedded Systems Design 57(6): 625-637 (2011)
Pascal Montag, Sebastian Altmeyer: Precise WCET calculation in highly variant real-time systems. DATE 2011: 920-925
Ernst Althaus, Sebastian Altmeyer, Rouven Naujoks: Symbolic Worst Case Execution Times. ICTAC 2011: 25-44
Ernst Althaus, Sebastian Altmeyer, Rouven Naujoks: Precise and efficient parametric path analysis. LCTES 2011: 141-150
Sebastian Altmeyer, Claire Maiza: Cache-related preemption delay via useful cache blocks: Survey and redefinition. Journal of Systems Architecture - Embedded Systems Design 57(7): 707-719 (2011)
Christoph Cullmann: Cache persistence analysis: a novel approachtheory and practice. LCTES 2011: 121-130
Gernot Gebhard, Christoph Cullmann, Reinhold Heckmann: Software Structure and WCET Predictability. PPES 2011: 1-10
Sebastian Altmeyer, Robert Davis and Claire Maiza: Cache-Related Pre-Emption Delay Aware Response Time Analysis For Fixed Priority Pre-Emptive Systems, IEEE RTSS, Vienna 2011
4.6.2Tool or Platform: WCC
WCC is the leading WCET-aware compiler. The WCET analyzer aiT has been tightly integrated into the compiler.
In the course of ArtistDesign, WCC has matured and is currently evaluated in an industrial context. WCC’s single-task WCET-aware optimizations developed during ArtistDesign are able to outperform well-established compilers like e.g. the GCC. First steps towards WCET-aware compilation for multi-task systems are made, more work in this area and towards support of multi-core systems will be done in the near future.
The current work explores the optimization potential of WCC and extends it towards multi-task and multi-core systems.
TU Dortmund integrates aiT into WCC and explores the optimization potential.
Related Publications Heiko Falk and Helena Kotthaus. WCET-driven Cache-aware Code Positioning. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pages 145-154, Taipei, Taiwan, October 2011 (best paper candidate)
Sascha Plazar, Jan C. Kleinsorge, Heiko Falk and Peter Marwedel. WCET-driven Branch Prediction aware Code Positioning. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pages 165-174, Taipei, Taiwan, October 2011.
Jan C. Kleinsorge, Heiko Falk and Peter Marwedel. A Synergetic Approach To Accurate Analysis Of Cache-Related Preemption Delay. In Proceedings of the International Conference on Embedded Software (EMSOFT), pages 329-338, Taipei, Taiwan, October 2011.
Samarjit Chakraborty, Marco Di Natale, Heiko Falk, Martin Lukasiewyzc and Frank Slomka. Timing and Schedulability Analysis for Distributed Automotive Control Applications. In Tutorial at the International Conference on Embedded Software (EMSOFT), pages 349-350, Taipei, Taiwan, October 2011.
Heiko Falk, Norman Schmitz and Florian Schmoll. WCET-aware Register Allocation based on Integer-Linear Programming. In Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS), pages 13-22, Porto / Portugal, July 2011.
Paul Lokuciejewski, Sascha Plazar, Heiko Falk, Peter Marwedel and Lothar Thiele. Approximating Pareto optimal compiler optimization sequences---a trade-off between WCET, ACET and code size. Software: Practice and Experience, May 2011. DOI 10.1002/spe.1079
4.6.3Tool or Platform : MAST
The main objective of MAST is to provide a model to describe the timing behaviour of real-time applications, in such a way that automatic schedulability analysis can be performed to assess the ability of the application to meet all of its timing requirements. Also an objective is that this real-time model can be obtained from a more detailed design model described, for instance, in MARTE, the UML profile for real-time embedded systems.
MAST defines a model to describe the timing behaviour of real-time systems designed to be analysable via schedulability analysis techniques. MAST also provides an open-source set of tools to perform schedulability analysis or other timing analysis, with the goal of assessing whether the system will be able to meet its timing requirements, and, via sensitivity analysis, how far or close is the system from meeting its timing requirements. Tools are also provided to help the designer in the assignment of scheduling parameters. By having an explicit model of the system and automatic analysis tools it is also possible to perform design space exploration. A discrete event simulator is also provided to obtain statistical performance information of the modelled system.
The original MAST model is now being enhanced to accommodate new modelling capabilities, partition-based scheduling as one of the base policies to use in the hierarchical scheduling modelling capabilities, support for clock synchronization, and support for resource reservation techniques. The new model is called MAST-2. The discrete event simulator has been redesign to accommodate the new MAST-2 model, and the schedulability analysis tools are being updated.
University of Cantabria
4.6.4Tool or Platform : MPA (Modular Performance Analysis)
The tool MPA (modular performance analysis) is based on an extension of network calculus that is termed real-time calculus (RTC). The purpose of the tool is to perform an end-to-end real-time analysis of complex distributed embedded systems. The implementation is based on a Java mathematical library for max-+ algebra with an associated Matlab interface.
Within ARTISTDesign, the MPA tool box has been (a) extended towards the new results together with University Braunschweig (TUBS) related to hierarchical event streams and (b) it has been linked to the Symta/S tool suite as described above. In addition, the toolbox has been used in the context of various application studies from avionic and automotive domain.
In the 4th year of ARTISTDesign, the toolbox has been linked to other performance analysis frameworks, in partciular UPPAAL from Uppsala University (Wang Yi, Bengt Jonsson). Some first promising results are available already. Especially, we have been investigating the interaction of memory accesses on the bus- and memory system of multi-core platforms. To this end, we developed a block-based representation of applications (super-block- model) and analysed the worst-case response time of corresponding tasks.
In addition, we used the method to investigate the interaction between memory access and computations in MPSoC platforms. This work has been undertaken together with University Saarland (Reinhard Wilhelm). In particular, the WCET analysis results have been used to calibrate the higher level performance analysis, i.e. to determine (a) worst case cycle counts for processing and (b) worst-case memory accesses.
All the corresponding interfaces and analysis methods have been implemented in the toolbox in the 4th year of ARTISTDesign and are now openly available.
The MPA toolbox has reached a certain level of maturity. It is in use for education and has been central to several international projects like SHAPES and COMBEST. It will be extended on demand with new functions, especially for the analysis of mixed criticality systems.
ETHZ: Provides and maintains the MPA toolbox
TUBS: Link to the Symta/S tool suite, development of algorithms and methods for hierarchical event stream analysis.
ETHZ: Kai Lampka, Simon Perathoner, Lothar Thiele: Analytic Real-Time Analysis and Timed Automata: A Hybrid Method for Analyzing Embedded Real-Time Systems. 8th ACM & IEEE International conference on Embedded software, EMSOFT 2009, CD edition, ACM, Grenoble, France, pages 107-116, October, 2009.
ETHZ: Lothar Thiele, Nikolay Stoimenov: Modular Performance Analysis of Cyclic Dataflow Graphs. EMSOFT 09: Proceedings of the 9th ACM international conference on Embedded software, Grenoble, France, pages 127-136, October, 2009.
ETHZ & TUBS: Simon Perathoner, Ernesto Wandeler, Lothar Thiele, Arne Hamann, Simon Schliecker, Rafik Henia, Razvan Racu, Rolf Ernst, Michael González Harbour: Influence of Different Abstractions on the Performance Analysis of Distributed Hard Real-Time Systems Design Automation for Embedded Systems, Springer Science+Business Media, LLC, Vol. 13, No. 1, pages 27-49, June, 2009.
ETHZ & TUBS: Simon Perathoner, Tobias Rein, Lothar Thiele, Kai Lampka and Jonas Rox: Modeling Structured Event Streams in System Level Performance Analysis, submitted to Conference on Languages, Compilers, and Tools for Embedded Systems LCTES, Stockholm, Sweden, April 2010
4.6.5Tool or Platform : MPARM
MPARM is a virtual SoC platform based on the SystemC simulation kernel, which could be used to model both HW and SW of complex systems. It has been developed by UNIBO for the past 7 years and has been shared with more than 20 research partners, who have substantially contributed to its evolution.
The classical system architecture simulated by the default MPARM distribution was represented so far by a homogeneous multicore system based on shared bus communication.
During the last year, MPARM has been enhanced with several HW parametric and customizable models, namely a new ARM11 ISS fully Harvard-architecure (i.e. with separated ports for data and instruction paths), a logarithmic interconnect crossbar, an accurate NoC model, a multi-ported L1 scratchpad memory, a DRAM controller (based on DRASIM2).
MPARM is now capable of simulating cluster-based manycore platforms, i.e. composed by several computation tiles (or clusters) connected via a mesh NoC. The computation tiles are supposed to be homogeneous and consist of a variable number of ARM11 cores, L1 instruction caches, a L1 multiport scratchpad memory for data, a DRAM memory controller, a network interface, a logarithmic crossbar, a set of devices for efficient intra-tile synchronization and a variable number of core tiles.