Advanced Configuration and Power Interface Specification Hewlett-Packard Corporation
Table 5-37 Static Resource Affinity Table Format
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- Processor Local APIC/SAPIC Affinity Structure
- Table 5-38 Processor Local APIC/SAPIC Affinity Structure
- Table 5-39 Flags – Processor Local APIC/SAPIC Affinity Structure
- Memory Affinity Structure
- Table 5-40 Memory Affinity Structure
- Table 5-41 Flags – Memory Affinity Structure
- Processor Local x2APIC Affinity Structure
- Table 5-42 Processor Local x2APIC Affinity Structure
- System Locality Distance Information Table (SLIT)
- Table 5-43 SLIT Format
- Corrected Platform Error Polling Table (CPEP)
- Table 5-44 Corrected Platform Error Polling Table Format
- Corrected Platform Error Polling Processor Structure
Table 5-37 Static Resource Affinity Table Format
The Processor Local APIC/SAPIC Affinity structure provides the association between the APIC ID or SAPIC ID/EID of a processor and the proximity domain to which the processor belongs. Table 5-38 provides the details of the Processor Local APIC/SAPIC Affinity structure. Table 5-38 Processor Local APIC/SAPIC Affinity Structure
Table 5-39 Flags – Processor Local APIC/SAPIC Affinity Structure
The Memory Affinity structure provides the following topology information statically to the operating system:
Table 5-40 provides the details of the Memory Affinity structure. Table 5-40 Memory Affinity Structure
Table 5-41 Flags – Memory Affinity Structure
The Processor Local x2APIC Affinity structure provides the association between the local x2APIC ID of a processor and the proximity domain to which the processor belongs. Table 5-42 provides the details of the Processor Local x2APIC Affinity structure. Table 5-42 Processor Local x2APIC Affinity Structure
This optional table provides a matrix that describes the relative distance (memory latency) between all System Localities, which are also referred to as Proximity Domains. Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources including for example, processors, memory, and I/O buses, that comprise what is known as a “NUMA node”. Processor accesses to memory or I/O resources within the local NUMA node is generally faster than processor accesses to memory or I/O resources outside of the local NUMA node. The value of each Entry[i,j] in the SLIT table, where i represents a row of a matrix and j represents a column of a matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality j in the system (including itself). The i,j row and column values correlate to the value returned by the _PXM object in the ACPI namespace. See section 6.2.12, “_PXM (Proximity)” for more information. The entry value is a one-byte unsigned integer. The relative distance from System Locality i to System Locality j is the i*N + j entry in the matrix, where N is the number of System Localities. Except for the relative distance from a System Locality to itself, each relative distance is stored twice in the matrix. This provides the capability to describe the scenario where the relative distances for the two directions between System Localities is different. The diagonal elements of the matrix, the relative distances from a System Locality to itself are normalized to a value of 10. The relative distances for the non-diagonal elements are scaled to be relative to 10. For example, if the relative distance from System Locality i to System Locality j is 2.4, a value of 24 is stored in table entry i*N+ j and in j*N+ i, where N is the number of System Localities. If one locality is unreachable from another, a value of 255 (0xFF) is stored in that table entry. Distance values of 0-9 are reserved and have no meaning. Table 5-43 SLIT Format
Platforms may contain the ability to detect and correct certain operational errors while maintaining platform function. These errors may be logged by the platform for the purpose of retrieval. Depending on the underlying hardware support, the means for retrieving corrected platform error information varies. If the platform hardware supports interrupt-based signaling of corrected platform errors, the MADT Platform Interrupt Source Structure describes the Corrected Platform Error Interrupt (CPEI). See section 5.2.11.14,”Platform Interrupt Source Structure”. Alternatively, OSPM may poll processors for corrected platform error information. Error log information retrieved from a processor may contain information for all processors within an error reporting group. As such, it may not be necessary for OSPM to poll all processors in the system to retrieve complete error information. This optional table provides information that allows OSPM to poll only the processors necessary for a complete report of the platform’s corrected platform error information. Table 5-44 Corrected Platform Error Polling Table Format
The Corrected Platform Error Polling Processor structure provides information on the specific processors OSPM polls for error information. Table 5-45 provides the details of the Corrected Platform Error Polling Processor structure. Directory: DOWNLOADS DOWNLOADS -> Northern England’s set-jetting locations DOWNLOADS -> Dynatest 3031 lwd light Weight Deflectometer DOWNLOADS -> Forth coming competitive exams DOWNLOADS -> Brush High School Morning Announcements Friday, September 05, 2014 all school DOWNLOADS -> Year 9 The Arts — Music DOWNLOADS -> Years 7 and 8 standard elaborations — Australian Curriculum: Music draft DOWNLOADS -> Chris Young sets 2016 “I’m Comin’ Over” Tour headlining dates DOWNLOADS -> Slavery and Abolition: the Plymouth Connection Introduction DOWNLOADS -> Summer Assignment Download 7.02 Mb. Share with your friends:
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