Arm processor September 2005 Introduction

As an enhancement of the ARM610, the ARM 710 offers an increased cache size (8K rather than 4K), clock frequency increased to 40MHz, improved write buffer and larger TLB in the MMU.

Additionally, it supports CMOS/TTL inputs, Fastbus, and 3.3V power but these features are not used in the RiscPC.

The ARM7500 is a RISC based single-chip computer with memory and I/O control on-chip to minimise external components. The ARM7500 can drive LCD panels/VDUs if required, and it features power management. The video controller can output up to a 120MHz pixel rate, 32bit sound, and there are four A/D convertors on-chip for connection of joysticks etc.

The processor core is basically an ARM710 with a smaller (4K) cache.
The video core is a VIDC2.The IO core is based upon the IOMD.

The memory/clock system is very flexible, designed for maximum uses with minimum fuss. Setting up a system based upon the ARM7500 should be fairly simple.

  ARM 7500FE

A version of the ARM 7500 with hardware floating point support.

The StrongARM took the RiscPC from around 40MHz to 200-300MHz and showed a speed boost that was more than the hardware should have been able to support. Still severely bottlednecked by the memory and I/O, the StrongARM made the RiscPC fly. The processor was the first to feature different instruction and data caches, and this caused quite a lot of self-modifying code to fail including, amusingly, Acorn's own runtime compression system. But on the whole, the incompatibilities were not more painful than an OS upgrade (anybody remember the RISC OS 2 to RISC OS 3 upgrade, and all the programs that used SYS OS_UpdateMEMC, 64, 64 for a speed boost froze the machine solid!).

In instruction terms, the StrongARM can offer half-word loads and stores, and signed half-word and byte loads and stores. Also provided are instructions for multiplying two 32 bit values (signed or unsigned) and replying with a 64 bit result. This is documented in the ARM assembler user guide as only working in 32-bit mode, however experimentation will show you that they work in 26-bit mode as well.

Later documentation confirms this. The cache has been split into separate instruction and data cache (Harvard architecture), with both of these caches being 16K, and the pipeline is now five stages instead of three.

In order to squeeze the maximum from a RiscPC, the Kinetic includes fast RAM on the processor card itself, as well as a version of RISC OS that installs itself on the card. Apparently it flies due to removing the memory bottleneck, though this does cause 'issues' with DMA expansion cards.

This is a version of the SA110 designed primarily for portable applications. I mention it here as I am reliably informed that the SA1100 is the processor inside the 'faster' Panasonic satellite digibox. It contains the StrongARM core, MMU, cache, PCMCIA, general I/O controller (including two serial ports), and a colour/greyscale LCD controller. It runs at 133MHz or 200MHz and it consumes less than half a watt of power.

  Thumb

The Thumb instruction set is a reworking of the ARM set, with a few things omitted. Thumb instructions are 16 bits (instead of the usual 32 bit). This allows for greater code density in places where memory is restricted. The Thumb set can only address the first eight registers, and there are no conditional execution instructions. Also, the Thumb cannot do a number of things required for low-level processor exceptions, so the Thumb instruction set will always come alongside the full ARM instruction set. Exceptions and the like can be handled in ARM code, with Thumb used for the more regular code.

This is an extension of the version three designs (ARM 6 and ARM 7) that provides the extended 64 bit multiply instructions. These instructions became a main part of the instruction set in the ARM version 4 (Strong-Arm, etc).

These processors include the Thumb instruction set (and, hence, no 26 bit mode).

These processors include a number of additional instructions which provide improved performance in typical DSP applications. The 'E' standing for "Enhanced DSP".

 

The future

The future is here. Newer ARM processors exist, but they are 32 bit devices. This means, basically, that RISC OS won't run on them until all of RISC OS is modified to be 32 bit safe. As long as BASIC is patched, a reasonable software base will exist. However all C programs will need to be recompiled. All relocatable modules will need to be altered. And pretty much all assembler code will need to be repaired. In cases where source isn't available (ie, anything written by Computer Concepts), it will be a tedious slog. It is truly one of the situations that could make or break the platform.

The ARM926EJ-S core incorporates the Jazelle instructions for Java acceleration. This is complemented by the Jazelle Support Code that manages the interface between the core hardware, the virtual machine and the operating system.

ARM have implemented a technology that allows certain of their architectures to execute Java byte code natively in hardware, in another execution mode alongside the existing ARM and Thumb modes and accessed in a similar fashion to ARM/Thumb interworking. The first processor with Jazelle technology was the ARM926EJ-S: Jazelle being denoted by the 'J' in the CPU name.

ARM Jazelle® technology for acceleration of execution environments provides our connected community with high quality, class leading solutions for the ARM architecture that offer the optimum combination of high performance, low power and low cost.ARM Jazelle DBX (Direct Byte code eXecution) technology for direct byte code execution of Java^TM delivers an unparalleled combination of Java performance and the world's leading 32-bit embedded RISC architecture - giving platform developers the freedom to run Java applications alongside established OS, middleware and application code on a single processor. The single-processor solution offers higher performance, lower system cost and lower power than coprocessors and dual-processor (dedicated Java processor and native applications processor) solutions.

ARM Jazelle RCT (Runtime Compilation Target) technology supports efficient ahead-of-time (AOT) and just-in-time (JIT) compilation with Java and other execution environments. By ensuring that techniques such as AOT and JIT can be implemented with up to 3x smaller memory footprint, Jazelle RCT technology enables high performance with a significant reduction in application memory footprint and power consumption. Jazelle RCT is applicable to Java and other execution environments such as Microsoft .NET Compact Framework. ARM’s Jazelle DBX and Jazelle RCT technologies offer flexibility and choice in a roadmap for efficient and high performance implementation of execution environments across a wide range of ARM platforms.

Thumb-2

Thumb-2 also extends both the ARM and Thumb instruction set with yet more instructions, including bit-field manipulation, table branches, and conditional execution.

Thumb-2EE

Thumb-2EE, marketed as Jazelle RCT, was announced in 2005, appearing in the Cortex series of cores. Thumb-2EE provides a small extension to Thumb-2, making the instruction set particularly suited to code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. Thumb-2EE is a target for languages such as Java, C#, Perl and Python, and allows JIT compilers to output smaller compiled code without impacting performance. New features provided by Thumb-2EE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and the ability to branch to handlers, which are small sections of frequently called code, commonly used to implement a feature of a high level language, such as allocating memory for a new object.

NEON

NEON technology is a combined 64 and 128bit SIMD (Single Instruction Multiple Data) instruction set that provides standardized acceleration for media and signal processing applications. NEON can execute MP3 audio decoder in less than 10 CPU MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec using only 13 CPU MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single precision floating-point data and operates in SIMD operations for handling audio/video processing as well as graphics and gaming processing. SIMD is a crucial element in vector supercomputers which feature simultaneous multiple operations. In NEON, the SIMD supports up to 16 operations at the same time.

VFP

VFP technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation that is fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDA, smart phones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions allowing SIMD (Single Instruction Multiple Data) parallelism. This is useful in graphics and signal-processing applications by reducing code size and increasing throughput.

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