Chapter 1 Basic Principles of Digital Systems outlin e 1

(i.e., size of the internal transistors) that allows more efficient packaging and faster operation.

Low-voltage logic is particularly popular for battery-powered applications such as

laptop computing or cell phones. Low voltage families typically operate at VCC _ 3.3 V or

2.5 V. Newer devices are available for VCC _ 1.8 V or 1.65 V.

Low-voltage CMOS families such as 74LVX or 74LCX can interface directly with

TTL outputs if they are operated with a 3.0 V to 3.3 V power supply. These families are not

really suitable for driving 5-volt TTL, as their noise margins are too small when they use a

3.0 V supply voltage.

If we wish to use a 74LS device to drive a 74HC device operating at a power supply

voltage of less than 4.5 V, we can use a 74HC4049 or 74HC4050 buffer to translate the

TTL logic level down to an appropriate value. The 74HC4049 is a package of six inverting

buffers. The 74HC4050 has six noninverting buffers. These buffers can tolerate up to 15 V

on their inputs. Their output voltages are determined by the value of their supply voltage.

Figure 11.15 shows an LSTTL-to-74HC interface circuit with a 74HC4050 buffer.

Note that the interface buffer has the same power supply voltage as the load gate. Both

sides of the interface are referenced to the same ground.

GND

_ 5 V _ 3 V

74LS-to-74HC Interface Using a 74HC4050 Buffer

❘❙❚ SECTION 11.6 REVIEW PROBLEM

11.6 A 74LS00 driving gate is to be interfaced to a 74HC00 load using a 74HC4050 noninverting

buffer. The 74HC00 has a power supply voltage of 2.5 V. What supply voltage

should the 74HC4050 buffer have? Why?

current flowing and the path from collector to emitter is effectively an open circuit.

In a digital application, a transistor in cutoff mode is considered OFF.

Saturation mode The operating mode of a bipolar transistor when an increase in

base current will not cause a further increase in the collector current and the path

from collector to emitter is very nearly (but not quite) a short circuit. This is the ON

state of a transistor in a digital circuit.

TTL has been around for a long time. The first transistor-transistor logic ICs were developed

by Texas Instruments around 1965. Since then, there have been many improvements in the

speed and power consumption of these devices, but the basic logic principles remain largely

unchanged. Even though they are seldom used in modern designs, itmakes sense to examine

the internal circuitry of standard TTL gates such as the 7400 NAND, 7402 NOR, and 7404

inverter because the internal logic concepts are similar to the more advanced types of TTL.

The most important parts of the circuit, as far as a designer or technician is concerned,

are the input and output circuits, because they are the only parts of the chip to which we

have access. It is to these points that we interface other circuits and where we make diag-

K E Y T E R M S

nostic measurements. A basic understanding of the inputs and outputs of logic gate circuitry

is helpful when we design or troubleshoot a digital circuit.

Bipolar Transistors as Logic Devices

The basic element of a TTL device is the bipolar junction transistor, illustrated in Figure

11.16. This is not the place to give a detailed analysis of the operation of a bipolar transistor,

but a simplified summary of operating modes will be useful.

The bipolar transistor is a current amplifier having three terminals called the collector,

emitter, and base. Current flowing into the base controls the amount of current flowing

from the collector to the emitter. If base current is below a certain threshold, the transistor

is in cutoff mode and no current flows in the collector. In this state, the base-emitter

voltage is less than 0.6 V and the collector-emitter path acts like an open circuit. We can

treat the collector-emitter path as an open switch, as shown in the lefthand diagram in

Figure 11.17.

Currents and Voltages in an NPN

Bipolar Transistor

FIGURE 11.17

NPN Bipolar Transistor as a Switch

If the base current increases, the transistor enters the “active region,” where the collector

current is proportional to the base current by a current gain factor, b. This is the linear,

or amplification, region of operation, used by analog amplifiers.

If the base current increases still further, collector current reaches a maximum value

and will no longer increase with base current. This is called the saturation mode of the

transistor. The saturated value of collector current, ICS, is determined by (1) the resistance

in the collector-emitter current path, (2) the voltage drop across the collector and emitter,

not increase significantly with increasing base current. The voltage between collector and

emitter is in the range from 0.2 V to 0.5 V. In this mode, we can treat the transistor as a

closed switch, as shown in the righthand diagram of Figure 11.17.

Table 11.5 summarizes the voltages and currents in the cutoff, active, and saturation

regions.

❘❙❚ EXAMPLE 11.13 Figure 11.18 shows an NPN bipolar transistor connected in a common-emitter configuration.

With the right choice of input voltages, this circuit acts as a digital inverter.

FIGURE 11.18

Example 11.13

Transistor as Inverter

FIGURE 11.19

Example 11.13

Voltage and Current Analysis of Inverter

Analyze the circuit to show that it acts as an inverter if a logic HIGH is defined as

_3 V and a logic LOW is defined as _0.5 V. Assume that b _ 100, and assume that

VBE _ 0.7 V and VCE _ 0.2 V in saturation.

Solution We will analyze the circuit with two input voltages: 3 V (logic HIGH) and 0.5

V (logic LOW). These two conditions are shown in Figure 11.19.

that this is true and find out if calculations confirm our assumption.

Figure 11.19a shows the circuit with VI _ 3 V. By Kirchhoff’s voltage law (KVL):

VI _ IBRB _ VBE, or

IB _ (VI _ VBE)/RB

If we assume that IB is sufficient to saturate the transistor, then:

_ 105 _A

Collector current won’t increase beyond its saturated value, even if base current increases.

Therefore, if the transistor is saturated, bIB will be larger than the current actually

flowing in the collector-emitter path.

In saturation, the collector current can be calculated by KVL:

VCC _ IC RC _ VCE, or

IC _ (VCC _ VCE)/RC

IC _ (5 V _ 0.2 V)/470 _

_ 10.2 mA

Since bIB IC, the transistor is saturated. Thus, an input voltage of 3 V will produce

sufficient base current to saturate the transistor. The output is given by VO _ VCE _ 0.2 V,

which is within the defined range of a logic LOW.

LOW input. Figure 11.19b shows the circuit with VI _ 0.5 V. By KVL:

VI _ IB RB _ VBE

VBE _ 0.5 V _ IB RB

Since VBE must be _0.6 V, the transistor is in cutoff mode. Thus, in the collector circuit:

5 V _ (0)(470 _) _ VCE

Table 11.6 summarizes the operation of the circuit as an inverter.

Inverter

0.5 V LOW 5 V HIGH

3 V HIGH 0.2 V LOW

TTL Open-Collector Inverter and NAND Gate

transistor is brought out directly to the output pin. There is no built-in HIGHstate

output circuitry, which allows two or more open-collector outputs to be connected

without possible damage.

The TTL gates (7405, 7401, 7404, 7400, and 7402) used in the following sections

to illustrate TTL circuit principles are no longer in general use. They are from the

original (“standard”) TTL family, which has been superceded by faster and more

efficient devices. However, the standard TTL devices are easier to understand than

devices from the newer TTL subfamilies, since their circuit structure is simpler. The

operating principles are similar in both the standard and newer families, so we will

use the standard devices to illustrate the general principles of TTL operation.

Figure 11.20 shows the circuit of the simplest TTL gate: a 7405 inverter with open-collector

in Example 11.13. These circuits differ most obviously in their input circuitry. The

inverter circuit in Example 11.13 has a resistor as its input; the 7405 inverter has a transistor,

N O T E

is common to all standard TTL gates and will be examined in detail later in this section.

The logic function of the 7405 is performed by transistors Q2 and Q3. Output transistor

Q3 is switched ON and OFF by current flowing in the collector-emitter path of Q2.

When Q3 is ON, Y is LOW.

However, when Q3 is OFF, Y is floating. There is a high impedance between Y and

ground, so the output is not LOW. But there is no connection to VCC to make the output

HIGH. In this condition, Y is neither HIGH nor LOW.

To enable the output to produce a HIGH state, we need to add an external pull-up resistor.

The value of this resistor depends on the current sinking capability of Q3, specified

in the data sheet as IOL. We will do such calculations in a later example.

Transistor Q1 and diode D1 make up the input circuit of the TTL inverter of Figure 11.20.

The diode protects the input against small negative voltages. If the input goes more negative

than about _0.7 V, the diode will conduct, effectively short-circuiting the input to

ground plus one diode drop. This clamps the input to _0.7 V. D1 has no logic function.

Q1 can be treated as two back-to-back diodes, as shown in Figure 11.21. Figure 11.22

shows how the input responds to logic HIGH and LOW voltages.

forward-biased diode, creating a current path from VCC to ground via the input pin. This

Open-Collector Inverter (7405)

current makes up the majority of current IIL, which has a maximum value of 1.6 mA in

standard TTL (0.4mA in LSTTL).

At the moment the input is made LOW, the transistor action of Q1 transports charge

away from the base of Q2, pulling it LOW and keeping it in cutoff mode. This current dies

out when the base charge of Q2 has been depleted, shortly after the LOW is applied to the

input pin. The diode formed by the base-collector junction of Q1 does not carry sufficient

current to turn on Q2, since the base-emitter path is of much lower impedance.

Only a small leakage current, IIH, flows. The maximum value of IIH is 40 _A for standard

TTL (20 _A for LSTTL).

Since the low-impedance current path to the input pin has not been established, current

flows to the base of Q2 via the forward-biased base-collector junction of Q1. This current

is sufficient to saturate Q2.

by Figure 11.23. A TTL input relies on a logic LOW to establish a low-impedance

current path from VCC to the input pin. If the input is open, this LOW is not present and

current flows in the base-collector junction of the transistor, by default. This is the same

current that flows under the HIGH-input condition.

This HIGH is not stable; it can be converted to logic LOW by induced noise at the input

pin. To avoid this uncertainty, an unused input should always be wired to a logic HIGH

or LOW state.

Diode Equivalent of TTL Input

Transistor

FIGURE 11.22

HIGH and LOW Inputs at a

TTL Gate

524 C H A P T E R 1 1 • Logic Gate Circuitry

TTL Open-Collector Inverter

Figure 11.24 shows the operation of the 7405 open-collector inverter.

LOW, HIGH, and Open

TTL Inputs

FIGURE 11.24

7405 Operation

ground, which draws current through the base-emitter junction of Q1. This action also prevents

base current from flowing in transistor Q2, causing it to be in cutoff mode and making

IC2 _ 0.

Since IB3 is derived from IC2, IB3 _ 0 and Q3 is cut off, making a high-impedance path

between the collector and emitter of Q3. As was the case with the single-transistor inverter

in Example 11.13, when IC3 _ 0, then VO _ VCE _ VCC. (Since no current flows through

the pull-up resistor, the voltage must be the same at both ends.) Output Y is HIGH.

HIGH Input. When input A is HIGH, the base-emitter junction of Q1 does not have sufficient

voltage across it to be forward-biased. Current flows through the base-collector

junction of Q1, saturating Q2.

Since Q2 is ON, current flows to the Q2 emitter and splits through the 1-k_ resistor

and the base of Q3. The output transistor, Q3, turns ON, establishing a low-impedance current

path from output Y to ground. Current is limited by the external pull-up resistor, which

must be chosen to keep IOL at or under its rated value of 16 mA. VCE3 is about 0.2 V to 0.4

V. Output Y is LOW.

Figure 11.25 shows one gate of a 7401 quadruple 2-input NAND gate with open-collector

outputs. The circuit is the same as that of the 7405 inverter, except that the input transistor

has a second emitter. Multiple-emitter transistors of this type are common in TTL circuits

and can be modeled by the diode equivalent in Figure 11.25b. Figure 11.26 shows the response

of the multiple-emitter input transistor to various combinations of logic levels.

LOW input. (A low-impedance path is created through a base-emitter junction.) Output Y

for this condition is:

TTL NAND with Open Collector Output

Input Response of Multiple-Emitter Transistor

0 0 1

current path through the one grounded emitter prevents sufficient basecollector

current from flowing to forward-bias that junction. Output Y is HIGH if a pull-up

resistor is connected to the output. A partial truth table is as follows:

0 1 1

(There is no base-emitter current path. A collector-emitter path is established by default.)

1 1 0

0 0 1

1 0 1

Combining all these conditions, we get the standard NAND truth table:

If one or more emitters of a TTL multiple-emitter input transistor is LOW, the input

is a LOW equivalent. All emitters must be HIGH to make the transistor input a

HIGH equivalent.

These statements lead to the familiar NAND-gate descriptive sentences, illustrated by

the gate symbols in Figure 11.27.

a. At least one input LOW makes the output HIGH.

b. Both inputs HIGH make the output LOW.

N O T E

DeMorgan Equivalent Forms of a NAND Gate

❘❙❚ SECTION 11.7A REVIEW PROBLEM

11.7 What are the two main functions of the pull-up resistor on the output of an opencollector

gate?

Open-Collector Applications

together. The logical effect is the ANDing of connected functions.

A more common TTL output than the open collector is the totem pole output, which we

will study later in this chapter. The totem pole output has its own internal pull-up circuit for

HIGH outputs.

K E Y T E R M

Gates with totem pole outputs cannot be used in all digital circuits. For example, opencollector

gates are required when several outputs must be tied together, a connection called

wired-AND. Totem pole outputs would be damaged by such a connection, since there is

the possibility of conflict between an output HIGH and LOW state.

Open-collector outputs can also be used for applications requiring high current drive

and for interfacing to circuits having supply voltages other than TTL levels.

A special symbol defined by IEEE/ANSI Standard 91-1984, an underlined square diamond,

is shown in Figure 11.28. This symbol is added to a logic gate symbol to indicate

that it has an open-collector output. Other symbols, such as a star (*), a dot (●), or the initials

OC are also used.

A wired-AND connection combines the outputs of the connected gates in an AND

function.

N O T E

Open-Collector Symbols Shown

for a NAND Gate (e.g., 7401)

FIGURE 11.29

Three Inverters in a Wired-AND

Connection

Figure 11.29 shows three open-collector inverters connected in a wired-AND configuration.

The output transistors of the inverters are shown in Figure 11.30, with different

possible ON and OFF states. The only way output Y can remain HIGH is if all the transistors

are in their OFF states, as in Figure 11.30c. This can happen only if the outputs

of the inverters are all HIGH. This is the same as saying the outputs are ANDed together

at Y.

The Boolean expression for Y is:

_ A _ B _ C

By DeMorgan’s theorem, the wired-AND connection of inverter outputs is equivalent

to a NOR function. Because of this DeMorgan equivalence, the connection is sometimes

called “wired-OR.”

Figure 11.31 shows three NAND gates in a wired-AND connection. Since the output

functions are ANDed, the Boolean expression for Y is:

Y __AB __CD __EF

_ AB _ CD _ EF

The resulting function is called AND-OR-INVERT. Normally this requires at least

two types of logic gate—AND and NOR. The wired-AND configuration can synthesize

any size of AND-OR-INVERT network using only NAND gates.

The wired-AND function is sometimes shown as an AND symbol around a soldered

connection, as shown in Figure 11.31b.

Output Transistors of Open-

Collector Inverters in a Wired-

AND Connection

Standard TTL outputs have higher current ratings in the LOW state than in the HIGH state.

Thus, open-collector outputs are useful for driving loads that need more current than a standard

TTL output can provide in the HIGH state. There are special TTL gates with higher ratings

of IOL to allow even larger loads to be driven. Typical loads would be LEDs, incandescent

lamps, and relay coils, all of which require currents in the tens of milliamperes.

❘❙❚ EXAMPLE 11.14 A 74LS07 hex buffer/driver contains six noninverting buffers whose outputs are opencollector,

rated for IOLmax _ 40 mA and VOHmax _ 30 V. That is, even though there is no

internal circuit to provide a logic HIGH at the output, the output transistor can withstand a

voltage of up to 30 V without damage.

Figure 11.32 shows a 74LS07 buffer driving an incandescent lamp rated at 24 V, with a

resistance of 690 _. Calculate the current that flows when the lamp is illuminated. What

logic level at A turns the lamp on? Could the lamp be driven by a 74LS05 inverter? Why or

why not?

By KVL: 24 V _ (IOL)(690 _) _ VOL _ 0

Thus, IOL _ (24 V _ 0.7 V)/690 _ _ 33.8 mA

Since the buffer is noninverting, and current flows when the output of the 74LS07

sinks current to ground (LOW), the lamp is on when A is LOW.

A 74LS05 open-collector inverter would not be a suitable driver for the circuit for two

reasons: its output is only designed to withstand 5.5 V and it can only sink a maximum of

8 mA.