Chapter 1 Basic Principles of Digital Systems outlin e 1
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696 A P P E N D I X B • VHDL Language Reference assigned explicitly with the __ operator, or implicitly by inserting the user port name in the position of the corresponding port name within the component declaration.
__instance_name: __component_name GENERIC MAP (__parameter_name => __parameter_value , __parameter_name => __parameter_value) PORT MAP (__component_port => __connect_port, __component_port => __connect_port); ❘❙❚ EXAMPLES: —— Four Component Instantiation Statements —— Explicit port assignments adder1: full_add PORT MAP ( a => a(1), b => b(1), c_in => c0, c_out => c(1), sum => sum(1)); adder2: full_add PORT MAP ( a => a(2), b => b(2), c_in => c(1), c_out => c(2), sum => sum(2)); adder3: full_add PORT MAP ( a => a(3), b => b(3), c_in => c(2), c_out => c(3), sum => sum(3)); adder4: full_add PORT MAP ( a => a(4), b => b(4), c_in => c(3), c_out => c4, sum => sum (4)); —— Four component instantiations —— Implicit port assignments adder1: full_add PORT MAP (a(1), b(1), c0, c(1), sum(1)); adder2: full_add PORT MAP (a(2), b(2), c(1), c(2), sum(2)); adder3: full_add PORT MAP (a(3), b(3), c(2), c(3), sum(3)); adder4: full_add PORT MAP (a(4), b(4), c(3), c4, sum(4)); ❘❙❚ 2.4.3 Generic Clause A generic clause allows a component to be designed with one or more unspecified properties (“parameters”) that are specified when the component is instantiated. A parameter specified in a generic clause must be given a default value with the :_ operator. Syntax: —— parameters defined in entity declaration of component file ENTITY entity_name IS GENERIC(__parameter_name : type := __default_value; A P P E N D I X B • VHDL Language Reference 697 __parameter_name : type := __default_value); PORT (port declarations); END entity name; —— Component declaration in top-level file also has generic clause. —— Default values of parameters not specified. COMPONENT component_name IS GENERIC(__parameter_name : type; __parameter_name : type); PORT (port declarations); END COMPONENT; —— Parameters specified in generic map in component instantiation __instance_name: __component_name GENERIC MAP (__parameter_name => __parameter_value, __parameter_name => __parameter_value) PORT MAP (port instantiations); ❘❙❚ EXAMPLE: —— Component: behaviorally defined shift register —— with default width of 4. ENTITY srt_bhv IS GENERIC (width : POSITIVE := 4); PORT( serial_in, clk : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0)); END srt_bhv; ARCHITECTURE right_shift of srt_bhv IS BEGIN
PROCESS (clk) BEGIN
IF (clk’EVENT and clk = ‘1’) THEN q(width-1 downto 0) <= serial in & q(width-1 downto 1); END IF; END PROCESS; END right_shift; —— srt8_bhv.vhd —— 8-bit shift register that instantiates srt_bhv LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srt8_bhv IS PORT( data_in, clock : IN STD_LOGIC; qo : BUFFER STD_LOGIC_VECTOR(7 downto 0)); END srt8_bhv; ARCHITECTURE right shift of srt8_bhv IS —— component declaration COMPONENT srt_bhv GENERIC (width : POSITIVE); PORT( serial_in, clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 downto 0)); 698 A P P E N D I X B • VHDL Language Reference END COMPONENT; (example continues) BEGIN
—— component instantiation Shift_right_8: srt_bhv GENERIC MAP (width=> 8) PORT MAP (serial_in => data_in, clk => clock, q => qo); END right_shift; ❘❙❚
Agenerate statement is used to create multiple instances of a particular hardware structure. It relies on the value of one or more index variables to create the required number of repetitions.
__generate_label: FOR __index_variable IN __range GENERATE __statement; __statement; END GENERATE; ❘❙❚ EXAMPLES: —— Instantiate four full adders adders:
FOR i IN 1 to 4 GENERATE adder: full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i)); END GENERATE; —— Instantiate four latches from MAX+PLUS II primitives —— Requires the statements LIBRARY altera; and —— USE altera.maxplus.ALL; latch4: FOR i IN 3 downto 0 GENERATE latch_primitive: latch PORT MAP (d => d_in(i), ena => enable, q => q_out (i)); END GENERATE; ❘❙❚
A process is a concurrent statement, but the statements inside the process are sequential. For example, a process can define a flip-flop, a separate component whose ports are affected concurrently, but the inside of the flip-flop acts sequentially. A process executes all statements inside it when there is a change of a signal in its sensitivity list. The process label is optional. Syntax: __process_label: PROCESS (sensitivity list) variable declarations BEGIN sequential statements A P P E N D I X B • VHDL Language Reference 699 END PROCESS __process_label; ❘❙❚ EXAMPLE: —— D latch PROCESS (en) BEGIN IF (en = ‘1’) THEN q <= d; END IF;
END PROCESS; ❘❙❚ 3. Sequential Structures 3.1. If Statement 3.1.1. Evaluating Clock Functions 3.2. Case Statement A sequential structure in VHDL is one in which the order of statements affects the operation of the circuit. It can be used to implement combinational circuits, but is primarily used to implement sequential circuits such as latches, counters, shift registers, and state machines. Sequential statements must be contained within a process.
An IF statement executes one or more statements if a Boolean condition is satisfied. Syntax: IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE
__statement; __statement; END IF; ❘❙❚ EXAMPLE: PROCESS (reset, load, clock) VARIABLE count INTEGER RANGE 0 TO 255; BEGIN
IF (reset = ‘0’) THEN q <= 0;
ELSIF (reset = ‘1’ and load = ‘0’) THEN q <= p;
ELSIF (clock’EVENT and clock = ‘1’) THEN count := count + 1; q <= count; END IF;
700 A P P E N D I X B • VHDL Language Reference END PROCESS; ❘❙❚ 3.1.1 Evaluating Clock Functions As implied in previous examples, the state of a system clock can be checked with an IF statement using the predefined attribute called EVENT. The clause clock’EVENT (“clock tick EVENT”) is true if there has been activity on the signal called clock. Thus (clock’EVENT and clock _ ‘1’) is true just after a positive edge on clock.
A case statement is used to execute one of several sets of statements, based on the evaluation of a signal.
CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; ❘❙❚ EXAMPLES: —— Case evaluates 2-bit value of s and assigns —— 4-bit values of x and y accordingly —— Default case (others) required if using STD_LOGIC CASE s IS WHEN “00” => y <= “0001”; x <= “1110”; WHEN “01” => y <= “0010”; x <= “1101”; WHEN “10” => y <= “0100”; x <= “1011”; WHEN “11” => y <= “1000”; x <= “0111”; WHEN others => y <= “0000”; A P P E N D I X B • VHDL Language Reference 701 x <= “1111”; END CASE; —— This case evaluates the state variable “sequence” —— that can have two possible values: “start” and “continue” —— Values of out1 and out2 are also assigned for each case. CASE sequence IS WHEN start => IF in1 = ‘1’ THEN sequence <= start; out1 <= ‘0’; out2 <= ‘0’; ELSE sequence <= continue; out1 <= ‘1’; out2 <= ‘0’; END IF; WHEN continue => sequence <= start; out1 <= ‘0’; out2 <= ‘1’; END CASE; ❘❙❚ A P P E N D I X C ❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚ Manufacturers’ Data Sheets Data Sheet List
74LS00 Quad 2-input NAND Gate Motorola/sn74ls00rev6.pdf 703 74LS02 Quad 2-input NOR Gate Motorola/sn74ls02rev5.pdf 705 74LS04 Hex Inverter Motorola/sn74ls04rev6.pdf 707 74LS05 Hex Inverter (Open Collector) Motorola/sn74ls05rev6.pdf 709 74LS06/16 Hex Inverting Buffer (Open Collector) Texas Instruments/sdls020a.pdf 711 75LS07 Hex Noninverting Buffer (Open Collector) Texas Instruments/sdls021a.pdf 714 74LS08 Quad 2-input AND Gate Motorola/sn74ls08rev6.pdf 717 74LS32 Quard 2-input OR Gate Motorola/sn74ls32rev6.pdf 719 74LS86 Quard 2-input XOR Gate Motorola/sn74ls86rev6.pdf 721 74F00 Quad 2-input NAND Gate Texas Instruments/sdfs035a.pdf 723 74AS/ALS00 Quad 2-input NAND Gate Texas Instruments/sdas187a.pdf 726 74HC00 Quad 2-input NAND Gate Motorola/mc74hc00arev7a.pdf 731 74HCT00 Quad 2-input NAND Gate (TTL Input Levels) Motorola/mc74hct00arev6.pdf 735 74VHC00 Quad 2-input NAND Gate Motorola/mc74vhc00arev0.pdf 738 74VHCT00 Quad 2-input NAND Gate (TTL Input Levels) Motorola/mc74vhct00arev0.pdf 741 74HCU04 Hex Inverter (Unbuffered) Motorola/mc74hcu04arev1.pdf 744 74HC4049/4050 Hex Buffer Motorola/mc74hc4049rev6.pdf 749 74LVX00 Quad 2-input NAND Gate Motorola/mc74lvx00rev0b.pdf 753 74LCX00 Quad 2-input NAND Gate Motorola/mc74lcx00rev1.pdf 756 MC14XXXB 4000B-series CMOS Gates Motorola/mc14001brev3.pdf 759
14 13 12 11 10 9 1 2 3 4 5 6 VCC
8 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.75 5.0 5.25 V TA Operating Ambient Temperature Range 0 25 70 C IOH Output Current High 0.4 mA IOL Output Current Low 8.0 mA
14 1 14 1
ORDERING INFORMATION SN74LS04N 14 Pin DIP 2000 Units/Box SN74LS04D 14 Pin 2500/Tape & Reel
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8
V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, Out ut VIN = VIL or VIH 0.35 0.5 V IOL = 8.0 mA per Truth Table IIH Input HIGH Current 20 A VCC = MAX, VIN = 2.7 V In ut 0.1 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current 0.4 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX Power Supply Current ICC Total, Output HIGH 2.4 mA VCC = MAX Total, Output LOW 6.6 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
tPLH TurnOff Delay, Input to Output 9.0 15 ns VCC = 5.0 V tPHL TurnOn Delay, Input to Output 10 15 ns CC
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Base Byte Addresses Address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 80 83 86 89 8C 8F 92 95 98 9C 9F A2 A5 A8 AB AE 0010 B0 B3 B6 B9 BC BF C1 C4 C7 C9 CC CE D1 D3 D5 D8 0020 DA DC DE E0 E2 E4 E6 E8 EA EC ED EF F0 F2 F3 F5 0030 F6 F7 F8 F9 FA FB FC FC FD FE FE FF FF FF FF FF 0040 FF FF FF FF FF FF FE FE FD FC FC FB FA F9 F8 F7 0050 F6 F5 F3 F2 F0 EF ED EC EA E8 E6 E4 E2 E0 DE DC 0060 DA D8 D5 D3 D1 CE CC C9 C7 C4 C1 BF BC B9 B6 B3 0070 B0 AE AB A8 A5 A2 9F 9C 98 95 92 8F 8C 89 86 83 0080 7F 7C 79 76 73 70 6D 6A 67 63 60 5D 5A 57 54 51 0090 4F 4C 49 46 43 40 3E 3B 38 36 33 31 2E 2C 2A 27 00A0 25 23 21 1F 1D 1B 19 17 15 13 12 10 0F 0D 0C 0A 00B0 09 08 07 06 05 04 03 03 02 01 01 00 00 00 00 00 00C0 00 00 00 00 00 00 01 01 02 03 03 04 05 06 07 08 00D0 09 0A 0C 0D 0F 10 12 13 15 17 19 1B 1D 1F 21 23 00E0 25 27 2A 2C 2E 31 33 36 38 3B 3E 40 43 46 49 4C 00F0 4F 51 54 57 5A 5D 60 63 67 6A 6D 70 73 76 79 7C 768 A P P E N D I X E • EPROM Data for a Digitial Function Generator 769 SQUARE
Base Byte Addresses Address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0100 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0110 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0120 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0130 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0140 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0150 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0160 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0170 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0180 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0190 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 TRIANGLE Base Byte Addresses Address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0200 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E 0210 A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 B6 B8 BA BC BE 0220 C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 D6 D8 DA DC DE 0230 E0 E2 E4 E6 E8 EA EC F0 F2 F4 F6 F8 FA FC FE 0240 FE FC FA F8 F6 F4 F2 F0 EE EC EA E8 E6 E4 E2 E0 0250 DE DC DA D8 D6 D4 D2 D0 CE CC CA C8 C6 C4 C2 C0 0260 BE BC BA B8 B6 B4 B2 B0 AE AC AA A8 A6 A4 A2 A0 0270 9E 9C 9A 98 96 94 92 90 8E 8C 8A 88 86 84 82 80 0280 7E 7C 7A 78 76 74 72 70 6E 6C 6A 68 66 64 62 60 0290 5E 5C 5A 58 56 54 52 50 4E 4C 4A 48 46 44 42 40 02A0 3E 3C 3A 38 36 34 32 30 2E 2C 2A 28 26 24 22 20 02B0 1E 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 00 02C0 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 02D0 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 02E0 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 02F0 62 64 66 68 6A 6C 6E 70 72 74 76 78 7A 7C 7E 80 SAWTOOTH
Base Byte Addresses Address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0300 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0310 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0320 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 0330 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 0340 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 0350 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 0360 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 0370 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 0380 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 0390 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F 03A0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF 03B0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF 03C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF 03D0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF 03E0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 03F0 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FD FF 770 A P P E N D I X E • EPROM Data for a Digital Function Generator E.2 C Program This program is also on the accompanying CD in the file \Student_Files\EPROM\EPROM.C. /* Hex File Generator * Written by: Ronan Capina and Robert Dueck * * This program is to create a hex file in a specific EPROM record format. * The EPROM is addressed in blocks of 256 bytes (8 address lines) by an 8 bit * counter to create a digital image of one of several waveform outputs. * Two additional address bits select one of four output functions. * When the EPROM data are run through a D/A Converter, they create an * analog waveform running at the frequency of the counter divided by 256. * The waveforms are sine, square, triangle, and sawtooth. * The record format is as follows. (Spaces are inserted only for clarity. * The actual record must have NO spaces.) * * : 10 0080 00 AF5F67F0602703E0322CFA92007780C3 61 * * (:Record Length = 10hex = 16dec) * (Address = 0080hex; location in EPROM of first data byte in record) * (Record type = 00 = data) * (16 data bytes = 32 hex digits) * (Checksum; Record Length + Address High byte + Address Low byte * + Record type + data bytes + Checksum = 00, after discarding carry) * * An END record is also required, having a similar format, except that * Record Type = 01 = END and there are no data bytes. Checksum is still * required. * eg. :00000001FF */ #include #include #include #include #include void Sawtooth(int); void triangle(int); void Square(int); int AddrByte(int Addr); int Chksum(int sum); void sine(int); char *HexString(int value); char *Hex = HULL; int Ampl; const double Pi = 3.141592654; int main(void) { FILE *fp; int Fcn =1, Linenum, sum, Byte, Addr = 0; char Record[256]; clrscr();
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