Figure 2 Flow for Setting up SCIF Asynchronous Mode

SH7780 Group

Example of Using the SCIF in Asynchronous Mode (Serial Data Transfer)

REJ06B0717-0100/Rev.1.00 March 2008 Page 8 of 25
2.4
Processing Sequence of Sample Program
Table 1 gives examples for setting SCIF-related registers. Figures 3 to 6 provide sample flowcharts of the main function and interrupt handling of the sample program.
Table 1 SCIF Setting
Register Name
Address
Setting
Function
Interrupt priority register 2
(INT2PRI2)
H'FFD4 0008 HF 0000
SCIF-ch0 interrupt priority level
31 Interrupt mask clear register
(INT2MSKCR)
H'FFD4 CH
SCIF-ch0 interrupt mask clear Port H control register (PHCR)
H'FFEA EH' FC80 PH to PH SCIF0 module functions Port H pull-up control register
(PHPUPR)
H'FFEA EH PH to PH pull-up off Serial mode register (SCSMR)
H'FFD8 0004 H' 0020 Asynchronous mode bit data Parity enabled (even parity)
1 stop bit Clock source Pck Serial control register (SCSCR)
H'FFD8 0008 H' 0078 Operating on internal clock
RXI, ERI, and BRI interrupts enabled
SCK pin used as a port Bit rate register (SCBBR)
H'FFD8 CH FIFO control register (SCFCR)
H'FFD8 0010 H' 0070
RDF flag trigger number 16
START
*
Set status register (SR)
Set SCIF (channel 0) operation main function
MD:
"1", privileged mode
BL:
"0", exeptions and interrupts are not blocked.
IMASK: Interrupt mask level = Note
* Since this program directly changes registers for peripheral functions, the MD bit (processing mode bit) is set to 1 (privileged mode).
If this bit is changed to "0" (user mode) and the function for setting operations is called, access to the registers for peripheral functions leads to an address error.

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