Iii bsc ecs 8085 microprocessor and applications unit I introduction to 8085

Mode 2

Status:

D7	D6	D5	D4	D3	D2	D1	D0
OBF-A-bar	INTE1(O/P) / ACK-A-BAR	IBF-A	INTE2(I/P) / STB-A-bAR	INTR-A	X	X	X

INTERFACING WITH INTEL 8251A (USART)

• 
  The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.
  

• 
  It supports the serial transmission of data.
  

• 
  It is packed in a 28 pin DIP.
  

• 
  The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.
  

• 
  It monitors the data flow.
  

• 
  This section has three registers and they are control register, status register and data buffer.
  

• 
  The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.
  

• 
  When C/D(low) is high, the control register is selected for writing control word or reading status word.
  

• 
  When C/D(low) is low, the data buffer is selected for read/write operation.
  

• 
  When the reset is high, it forces 8251A into the idle mode.
  

• 
  The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.
  

• 
  The transmitter section accepts parallel data from CPU and converts them into serial data.
  

• 
  The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.
  

• 
  hen output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.
  

• 
  If buffer register is empty, then TxRDY is goes to high.
  

• 
  If output register is empty then TxEMPTY goes to high.
  

• 
  The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.
  

• 
  The clock frequency can be 1,16 or 64 times the baud rate.
  

• 
  The receiver section accepts serial data and convert them into parallel data
  

• 
  The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.
  

• 
  When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.
  

• 
  If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.
  

• 
  The CPU reads the parallel data from the buffer register.
  

• 
  When the input register loads a parallel data to buffer register, the RxRDY line goes high.
  

• 
  The clock signal RxC (low) controls the rate at which bits are received by the USART.
  

• 
  During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.
  

• 
  During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.
  

• 
  The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.
  

• 
  This unit takes care of handshake signals for MODEM interface.
  

• 
  Read/Write control logic
  
• 
  Transmitter
  
• 
  Receiver
  
• 
  Data bus buffer
  
• 
  Modem control.
  

• Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor.

• The processor will check the interrupts always at the 2nd T-state of last machine cycle.

• If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.

• The vectored address of particular interrupt is stored in program counter.

• The processor executes an interrupt service routine (ISR) addressed in program counter.

• It returned to main program by RET instruction.

Types of Interrupts:

It supports two types of interrupts.

• Hardware

• Software

• The software interrupts are program instructions. These instructions are inserted at desired locations in a program.

• The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can be calculated as follows.

• Interrupt number * 8 = vector address

• For RST 5,5 * 8 = 40 = 28H

• Vector address for interrupt RST 5 is 0028H

The Table shows the vector addresses of all interrupts.



Hardware interrupts:

• 
  An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.
  

• 
  If the interrupt is accepted then the processor executes an interrupt service routine.
  

TRAP:

• 
  This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.
  

• 
  TRAP bas the highest priority and vectored interrupt.
  

• 
  TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.
  

• 
  In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
  

• 
  The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
  

• 
  There are two ways to clear TRAP interrupt.
  

               1.By resetting microprocessor (External signal)

               2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:

• 
  The RST 7.5 interrupt is a maskable interrupt.
  

• 
  It has the second highest priority.
  

• 
  It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.
  

• 
  Maskable interrupt. It is disabled by,
  

               1.DI instruction

               2.System or processor reset.

               3.After reorganization of interrupt.

• 
  Enabled by EI instruction.
  

• 
  The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized.
  

• 
  Maskable interrupt. It is disabled by,
  

   1.DI, SIM instruction

               2.System or processor reset.

               3.After reorganization of interrupt.

• 
  Enabled by EI instruction.
  

• 
  The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
  

• 
  INTR is a maskable interrupt. It is disabled by,
  

               2.System or processor reset.

• 
  Enabled by EI instruction.
  

• 
  Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR.
  

• 
  It has lowest priority.
  

• 
  It is a level sensitive interrupts.  ie. Input goes to high and it is necessary to maintain high state until it recognized.
  

• 
  The following sequence of events occurs when INTR signal goes high.
  

• 
  Status read-back command
  
• 
  Counter latch command
  
• 
  Read/write least significant bit (LSB) only, most significant bit (MSB) only, or LSB first then MSB
  
• 
  Six programmable counter modes
  
  • 
    Interrupt on terminal count
    
  • 
    Hardware retriggerable one-shot
    
  • 
    Rate generator
    
  • 
    Square wave mode
    
  • 
    Software-triggered strobe
    
  • 
    Hardware-triggered strobe (retriggerable)
    
• 
  Binary or binary coded decimal strobe
  
• 
  Developed in VHDL and synthesizes to approximately 5,000 gates
  
• 
  Functionally based on the Intel 82C54 device
  

Block Diagram

Figure 1 shows the block diagram for the 8254 programmable interval timer/counter megafunction.

Figure 1. Block Diagram

Description

The 8254 programmable interval time/counter megafunction is a high-performance function that is designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, and each counter may operate in a different mode. All modes are software programmable. The 8254 megafunction solves one of the most common problems in any microcomputer system: the generation of accurate time delays under software control. Instead of setting up timing loops in software, the 8254 megafunction can be programmed to match requirements by programming one of the counters for the desired delay.

Directory: images
images -> Pelan pentaksiran kursus
images -> Military callsign list as of dec 2010
images -> For Date: 02/01/2013 Friday Call Number Time Call Reason Action 13-768 0008 motor vehicle stop warning Issued
images -> New embedded S
images -> Creating Buy-In – Building Relationships
images -> Deadline: Saturday, March 12th, 2016
images -> News items from Raising Our Voices
images -> Last year four of the best Afrikaans Christian singers joined forces to tour Down Under with the production ‘Manne wat Glo’
images -> World-renowned vocal ensemble sweet honey in the rock
images -> Peoples Voice Café History

Download 0.51 Mb.

Share with your friends: