Advanced Configuration and Power Interface Specification Hewlett-Packard Corporation


Table 5-37   Static Resource Affinity Table Format



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Table 5-37   Static Resource Affinity Table Format

Field

Byte Length

Byte Offset

Description

Header










Signature

4

0

‘SRAT’. Signature for the System Resource Affinity Table.

Length

4

4

Length, in bytes, of the entire SRAT. The length implies the number of Entry fields at the end of the table

Revision

1

8

3

Checksum

1

9

Entire table must sum to zero.

OEMID

6

10

OEM ID.

OEM Table ID

8

16

For the System Resource Affinity Table, the table ID is the manufacturer model ID.

OEM Revision

4

24

OEM revision of System Resource Affinity Table for supplied OEM Table ID.

Creator ID

4

28

Vendor ID of utility that created the table.

Creator Revision

4

32

Revision of utility that created the table.

Reserved

4

36

Reserved to be 1 for backward compatibility

Reserved

8

40

Reserved

Static Resource Allocation Structure[n]

---

48

A list of static resource allocation structures for the platform. See section 5.2.16.1,”Processor Local APIC/SAPIC Affinity Structure”, section 5.2.16.2 “Memory Affinity Structure”, and section 5.2.16.3 “Processor Local x2APIC Affinity Structure”.




        1.    Processor Local APIC/SAPIC Affinity Structure

The Processor Local APIC/SAPIC Affinity structure provides the association between the APIC ID or SAPIC ID/EID of a processor and the proximity domain to which the processor belongs. Table 5-38 provides the details of the Processor Local APIC/SAPIC Affinity structure.

Table 5-38   Processor Local APIC/SAPIC Affinity Structure

Field

Byte Length

Byte Offset

Description

Type

1

0

0 Processor Local APIC/SAPIC Affinity Structure

Length

1

1

16

Proximity Domain [7:0]

1

2

Bit[7:0] of the proximity domain to which the processor belongs.

APIC ID

1

3

The processor local APIC ID.

Flags

4

4

Flags – Processor Local APIC/SAPIC Affinity Structure. See Table 5-39 for a description of this field.

Local SAPIC EID

1

8

The processor local SAPIC EID.

Proximity Domain [31:8]

3

9

Bit[31:8] of the proximity domain to which the processor belongs.

Clock Domain

4

12

The clock domain to which the processor belongs. See section 6.2.1, “_CDM (Clock Domain)”.

Table 5-39   Flags – Processor Local APIC/SAPIC Affinity Structure

Field

Bit Length

Bit Offset

Description

Enabled

1

0

If clear, the OSPM ignores the contents of the Processor Local APIC/SAPIC Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable them as necessary.

Reserved

31

1

Must be zero.

        1.    Memory Affinity Structure

The Memory Affinity structure provides the following topology information statically to the operating system:

  • The association between a range of memory and the proximity domain to which it belongs

  • Information about whether the range of memory can be hot-plugged.

Table 5-40 provides the details of the Memory Affinity structure.
Table 5-40   Memory Affinity Structure

Field

Byte Length

Byte Offset

Description

Type

1

0

1 Memory Affinity Structure

Length

1

1

40

Proximity Domain

4

2

Integer that represents the proximity domain to which the processor belongs

Reserved

2

6

Reserved

Base Address Low

4

8

Low 32 Bits of the Base Address of the memory range

Base Address High

4

12

High 32 Bits of the Base Address of the memory range

Length Low

4

16

Low 32 Bits of the length of the memory range.

Length High

4

20

High 32 Bits of the length of the memory range.

Reserved

4

24

Reserved.

Flags

4

28

Flags – Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged. Details in See Table 5-41.

Reserved

8

32

Reserved.

Table 5-41   Flags – Memory Affinity Structure

Field

Bit Length

Bit Offset

Description

Enabled

1

0

If clear, the OSPM ignores the contents of the Memory Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable then as necessary.

Hot Pluggable5

1

1

The information conveyed by this bit depends on the value of the Enabled bit.

If the Enabled bit is set and the Hot Pluggable bit is also set. The system hardware supports hot-add and hot-remove of this memory region

If the Enabled bit is set and the Hot Pluggable bit is clear, the system hardware does not support hot-add or hot-remove of this memory region.

If the Enabled bit is clear, the OSPM will ignore the contents of the Memory Affinity Structure



NonVolatile

1

2

If set, the memory region represents Non-Volatile memory

Reserved

29

3

Must be zero.




        1.    Processor Local x2APIC Affinity Structure

The Processor Local x2APIC Affinity structure provides the association between the local x2APIC ID of a processor and the proximity domain to which the processor belongs. Table 5-42 provides the details of the Processor Local x2APIC Affinity structure.

Table 5-42   Processor Local x2APIC Affinity Structure

Field

Byte Length

Byte Offset

Description

Type

1

0

2 Processor Local x2APIC Affinity Structure

Length

1

1

24

Reserved

2

2

Reserved – Must be zero

Proximity Domain

4

4

The proximity domain to which the logical processor belongs.

X2APIC ID

4

8

The processor local x2APIC ID.

Flags

4

12

Same as Processor Local APIC/SAPIC Affinity Structure flags. See Table 5-39 for a description of this field.

Clock Domain

4

16

The clock domain to which the logical processor belongs. See section 6.2.1, “_CDM (Clock Domain)”.

Reserved

4

20

Reserved.




      1.    System Locality Distance Information Table (SLIT)

This optional table provides a matrix that describes the relative distance (memory latency) between all System Localities, which are also referred to as Proximity Domains. Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources including for example, processors, memory, and I/O buses, that comprise what is known as a “NUMA node”. Processor accesses to memory or I/O resources within the local NUMA node is generally faster than processor accesses to memory or I/O resources outside of the local NUMA node.

The value of each Entry[i,j] in the SLIT table, where i represents a row of a matrix and j represents a column of a matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality j in the system (including itself).

The i,j row and column values correlate to the value returned by the _PXM object in the ACPI namespace. See section 6.2.12, “_PXM (Proximity)” for more information.

The entry value is a one-byte unsigned integer. The relative distance from System Locality i to System Locality j is the i*N + j entry in the matrix, where N is the number of System Localities. Except for the relative distance from a System Locality to itself, each relative distance is stored twice in the matrix. This provides the capability to describe the scenario where the relative distances for the two directions between System Localities is different.

The diagonal elements of the matrix, the relative distances from a System Locality to itself are normalized to a value of 10. The relative distances for the non-diagonal elements are scaled to be relative to 10. For example, if the relative distance from System Locality i to System Locality j is 2.4, a value of 24 is stored in table entry i*N+ j and in j*N+ i, where N is the number of System Localities.

If one locality is unreachable from another, a value of 255 (0xFF) is stored in that table entry. Distance values of 0-9 are reserved and have no meaning.



Table 5-43   SLIT Format

Field

Byte Length

Byte Offset

Description

Header










Signature

4

0

‘SLIT’. Signature for the System Locality Distance Information Table.

Length

4

4

Length, in bytes, of the entire System Locality Distance Information Table.

Revision

1

8

1

Checksum

1

9

Entire table must sum to zero.

OEMID

6

10

OEM ID.

OEM Table ID

8

16

For the System Locality Information Table, the table ID is the manufacturer model ID.

OEM Revision

4

24

OEM revision of System Locality Information Table for supplied OEM Table ID.

Creator ID

4

28

Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the ID for the ASL Compiler.

Creator Revision

4

32

Revision of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the revision for the ASL Compiler.

Number of System Localities

8

36

Indicates the number of System Localities in the system.

Entry[0][0]

1

44

Matrix entry (0,0), contains a value of 10.












Entry[0][Number of System Localities-1]

1




Matrix entry (0, Number of System Localities-1)

Entry[1][0]

1




Matrix entry (1,0)

……







……

Entry[Number of System Localities-1][Number of System Localities-1]

1




Matrix entry (Number of System Localities-1, Number of System Localities-1), contains a value of 10




      1.    Corrected Platform Error Polling Table (CPEP)

Platforms may contain the ability to detect and correct certain operational errors while maintaining platform function. These errors may be logged by the platform for the purpose of retrieval. Depending on the underlying hardware support, the means for retrieving corrected platform error information varies. If the platform hardware supports interrupt-based signaling of corrected platform errors, the MADT Platform Inter­rupt Source Structure describes the Corrected Platform Error Interrupt (CPEI). See section 5.2.11.14,”Platform Interrupt Source Structure”. Alternatively, OSPM may poll processors for corrected platform error information. Error log information retrieved from a processor may contain information for all processors within an error reporting group. As such, it may not be necessary for OSPM to poll all processors in the system to retrieve complete error information. This optional table provides information that allows OSPM to poll only the processors necessary for a complete report of the platform’s corrected platform error information.

Table 5-44   Corrected Platform Error Polling Table Format

Field

Byte Length

Byte Offset

Description

Header










Signature

4

0

‘CPEP’. Signature for the Corrected Platform Error Polling Table.

Length

4

4

Length, in bytes, of the entire CPET. The length implies the number of Entry fields at the end of the table

Revision

1

8

1

Checksum

1

9

Entire table must sum to zero.

OEMID

6

10

OEM ID.

OEM Table ID

8

16

For the Corrected Platform Error Polling Table, the table ID is the manufacturer model ID.

OEM Revision

4

24

OEM revision of Corrected Platform Error Polling Table for supplied OEM Table ID.

Creator ID

4

28

Vendor ID of utility that created the table.

Creator Revision

4

32

Revision of utility that created the table.

Reserved

8

36

Reserved, must be 0.

CPEP Processor Structure[n]

---

44

A list of Corrected Platform Error Polling Processor structures for the platform. See section 5.2.17.1,” Corrected Platform Error Polling Processor Structure”.




        1.    Corrected Platform Error Polling Processor Structure

The Corrected Platform Error Polling Processor structure provides information on the specific processors OSPM polls for error information. Table 5-45 provides the details of the Corrected Platform Error Polling Processor structure.


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