Interrupts types and classification Interrupt driven os interrupt handling Generic routine, interrupt vectors, interrupt chaining Interrupt implementation in the system Interrupt controller priorities, masks, reentrancy Silberschatz, Operating System

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Network Card

The signals could be different for different systems (edge triggered, level triggered, positive / negative logic).

The interrupt controller is a device which could be implemented on a separate chip or be included into a larger chipset together with the other devices.

The Programmable Interrupt Controller (PIC) Intel's original controller was done on a separate chip 8259A.

The modern Advanced Programmable Interrupt Controller (APIC) is a more complex one and is incorporated with more complex chipset (South Bridge).

Typically CPU blocks the interrupt mask for particular device while it serves the previous interrupt of the same device – to not have nested or recursive interrupts from one device.

The Priority Encoder helps us to block the interrupts from lower interrupt levels and allow the interrupts of higher level only.

The priority encoder takes the allowed interrupt and sends it to CPU with the interrupt ID. The interrupt line tells CPU that it should serve this interrupt and that the number of interrupt is equal to ID.
CPU stops what it’s doing now and runs the interrupt routine corresponding to the interrupt ID. There could be different interrupt routines for CD, Printer or Network Card.
Interrupt Disable bit – If this bit is setup then no interrupts allowed at all. The interrupt line is blocked fully.
NMI is not affected by Interrupt Disable bit. All Non Maskable Interrupts are allowed always.
System Calls setup some bits in Software Interrupt registers which then cause interrupt in usual way as the other interrupt sources.

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  Interrupts invoked with interrupt lines from devices
  
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  Interrupt controller chooses interrupt request to honor
  
  0. 
     Mask enables/disables interrupts
     
  1. 
     Priority encoder picks highest enabled interrupt
     
  2. 
     Software Interrupt Set/Cleared by Software
     
  3. 
     Interrupt identity specified with ID line
     
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  CPU can disable all interrupts with internal flag
  
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  Non-maskable interrupt line (NMI) can’t be disabled
  

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  The controller passes the interrupt request to CPU and the program flow shown on the below picture is interrupted.
  

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  The first what happened the pipeline should be drained – pipeline flush – to fully stop any activity initiated by the previous program.
  
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  PC is saved to use it later to return to the interrupted program.
  
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  All interrupts are disabled by setting Disable Interrupt bit.
  

In hardware we disable all interrupts but in software we change the priority of interrupts

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  We Raise the priority to prevent recursive infinite interrupts of the same device or of the same level.
  
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  But we cannot leave the system without interrupt service during whole interrupt service time that is why immediately after raising priority we reenable interrupts to be able to handle the higher level interrupts. This is done purely by software and the software can choose the hierarchy of levels of interrupts. Typically it will just turn off the mask of this device and reenable all the other devices masks.
  
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  Save registers – of the interrupted program
  
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  Dispatch to network packet receiver handler
  
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  Transfer packet to the Kernel buffer.
  
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  Restore registers.
  
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  Talk to device and clear the interrupt. Setup appropriate bits in device controller to inform that the interrupt is serviced and the device can send new interrupt.
  
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  Now we have to enable the interrupts again from this device but we do not want to do it in this routine. Because this routine could be interrupted immediately after enabling the interrupts.
  
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  That was why we again disable all interrupts
  
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  Then restore the priority preparing to accept new interrupts from the same devices but not yet allowing them.
  

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  Finally enable the interrupts by hardware in RTI (iret in x86, eret in MIPS) instruction.
  

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  An application that can properly handle this situation is said to be reentrant.
  
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  Code segments that do not operate properly when reentered are nonreentrant.
  

Consider the TIMER.ASM program in the previous section. This is an example of a nonreentrant program. Suppose that while executing the ISR, it is interrupted at the following point:

TimerISR endp

Suppose that, on the first invocation of the interrupt, MSEC contains 950 and Timer contains three. If a second interrupt occurs and the specified point above, ax will contain 1005. So the interrupt suspends the ISR and reenters it from the beginning. Note that Timer ISR is nice enough to preserve the ax register containing the value 1005. When the second invocation of Timer ISR executes, it finds that MSEC still contains 950 because the first invocation has yet to update MSEC. Therefore, it adds 55 to this value, determines that it exceeds 1000, increments Timer (it becomes four) and then stores five into MSEC.
Then it returns (by jumping to the next ISR in the int 1ch chain). Eventually, control returns the first invocation of the TimerISR routine. At this time (less than 55 msec after updating Timer by the second invocation) the TimerISR code increments the Timer variable again and updates MSEC to five. The problem with this sequence is that it has incremented the Timer variable twice in less than 55 msec.
Now you might argue that hardware interrupts always clear the interrupt disable flag so it would not be possible for this interrupt to be reentered. Furthermore, you might argue that this routine is so short, it would never take more than 55 msec to get to the noted point in the code above. However, you are forgetting something: some other timer ISR could be in the system that calls your code after it is done. That code could take 55 msec and just happen to turn the interrupts back on, making it perfectly possible that your code could be reentered.
The code between the

mov ax, MSEC

mov MSEC, ax