Project summary


Broader Impact of Proposed Research



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Broader Impact of Proposed Research


The ATAC project seeks to improve the programmability of large-scale multicore processors through a combination of architectural features and programming language development. This work has the potential to change the way multicore processors are designed and manufactured by demonstrating the value of integrated on-chip photonic devices. This will spur additional research in the area of on-chip photonics and speed the adoption of this innovative technology.

By making high-performance multicore programming easier, it also has the potential to solve an important challenge facing the computer industry today. Although processor manufacturers have realized that their future products must be multicore, no one has practical solution that allows the average programmer to harness the power of these processors. Without further advances in this area, only specially-trained expert programmers will be able write high-performance software. Thus, either application performance will cease to improve or software development costs will skyrocket as more highly-trained programmers are required. By simplifying programming, the ATAC architecture will allow the computer industry to continue to produce high-performance software using the existing base of programmers, even though the underlying hardware will be somewhat more sophisticated.

Besides the potential long-term benefits to the computer industry and thereby society at-large, this project will have a more immediate impact on the community of multicore researchers and educators. The results of our research will be published in main-stream journals and conferences, allowing acceptance or criticism from a large community of researchers and industry experts. In addition, we plan to make much of the infrastructure developed in our project publicly available for use by others. This includes our new API and languages as well as our multicore simulator in open-source form. Our simulator infrastructure will need to be flexible enough to model a variety of multicore architectures to allow comparisons between the ATAC design and other approaches. Therefore, it will be useful to many other multicore researchers who will be able to modify it for their own experiments. We hope that our simulator infrastructure will become the de-facto standard used by researchers across the world to create their own multicore simulators.

As with all of our previous projects, both graduate and undergraduate education will be an integral part of the ATAC project. Graduate students form the core of our research team, working closely with each other as well as faculty investigators, postdoctoral researchers, and industry experts. In addition to graduate students, we always include a number of undergraduates participating in MIT’s UROP (Undergraduate Research Opportunities) program. These graduates and undergraduates will be directly involved in the proposed work, learning the techniques and challenges of multicore system building and programming. In addition to directly involving students in research, this project will influence a larger group of students through graduate-level courses taught by the PIs at MIT. These courses typically include hot research topics and reflect the current research of the PIs, exposing student to cutting-edge ideas and tools, such as the massive multicore simulator. This project will thereby help train the next generation of multicore researchers, engineers, and programmers.



REFERENCES

  1. Communications Technology Roadmap, The Microphotonics Center, Massachusetts Institute of Technology, 2005. http://mph-roadmap.mit.edu/

  2. Anant Agarwal, “Raw Computation,'' Scientific American, vol. 281, no. 2, pp. 44-47, August 1999. http://cag.csail.mit.edu/raw/documents/RAW_Computation_SciAm.pdf

  3. Anant Agarwal.  “Limits on Interconnection Network Performance.'' IEEE Transactions on Parallel and Distributed Systems, October 1991.

  4. Michael Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.  “The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,'' IEEE Micro, April 2002. http://cag.csail.mit.edu/raw/documents/ieee-micro-2002.pdf

  5. Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal, “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,'' Proc. of the 31st International Symposium on Computer Architecture (ISCA’04), pp. 2-13, June 2004. http://cag.csail.mit.edu/raw/documents/raw_isca_2004.pdf

  6. Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal, “Baring it all to software: Raw machines,” IEEE Computer, pp. 86-93, September 1997. http://cag.csail.mit.edu/raw/documents/Waingold-Computer-1997.pdf

  7. Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Walter Lee, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Saman Amarasinghe, and Anant Agarwal, “A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,Proc. of the IEEE International Solid-State Circuits Conference, February 2003. http://cag.csail.mit.edu/raw/documents/isscc_2003_paper.pdf

  8. Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal, “Scalar Operand Networks: Design, Implementation, Analysis,” IEEE Transactions on Parallel and Distributed Systems (Special Issue on On-chip Networks), February 2005. Also available as MIT/CSAIL Technical Report MIT-CSAIL-TR-2004-038, June 2004. http://cag.csail.mit.edu/raw/documents/son-tm.pdf

  9. Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe, “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,” Proc. of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), October 4-7, 1998. http://cag.csail.mit.edu/raw/documents/Lee-ASPLOS-1998.pdf

  10. Theodoros Konstantakopoulos, Jonathan Eastep, James Psota, and Anant Agarwal, “Energy Scalability of On-Chip Interconnection Networks in Multicore Architectures,” MIT CSAIL Technical Report, November 2007. http://cag.csail.mit.edu/raw/documents/Konstantakopoulos-Energy-2007.pdf

  11. Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal, “Compiler Support for Scalable and Efficient Memory Systems,” IEEE Transactions on Computers (Special Issue on Advances in High Performance Memory Systems), vol. 50 no. 11, pp. 1234-47, Nov 2001. http://cag.csail.mit.edu/raw/documents/Barua-Computer01.pdf

  12. Matthew Frank, C. Andras Moritz, Benjamin Greenwald, Saman Amarasinghe, and Anant Agarwal, “SUDS: Primitive Mechanisms for Memory Dependence Speculation,” MIT/LCS Technical Memo LCS-TM-591, January 6, 1999.

  13. Michael Gordon, William Thies, and Saman Amarasinghe, “Exploiting Coarse-Grained Task, Data, and Pipeline Parallelism in Stream Programs,” Proc. of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, October, 2006. http://cag.lcs.mit.edu/commit/papers/06/gordon-asplos06.pdf

  14. Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Ken Mackenzie, and Donald Yeung, “The MIT Alewife Machine: Architecture and Performance,” Proc. of the 22nd International Symposium on Computer Architecture (ISCA’95), pp. 2-13, June 1995.

  15. Anant Agarwal, John Kubiatowicz, David Kranz, Beng-Hong Lim, Donald Yeung, Godfrey D'Souza, and Mike Parkin, “Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors,” IEEE Micro, pages 48-61, June 1993.

  16. V. Nguyen, T. Montalbo, C. Manolatou, A. Agarwal, C.-Y. Hong, J. Yasaitis, L. C. Kimerling, and J. Michel, "Silicon-based highly-efficient fiber-to-waveguide coupler for high index contrast systems," Applied Physics Letters, vol. 88, pp. 081112, 2006.

  17. K. K. Lee, D. R. Lim, D. Pan, C. Hoepfner, W.-Y. Oh, K. Wada, L. C. Kimerling, K. P. Yap, and M. T. Doan, "Mode transformer for miniaturized optical circuits," Optics Letters, vol. 30, pp. 498, 2005.

  18. S. Akiyama, M. A. Popovic, P. T. Rakich, K. Wada, J. Michel, H. A. Haus, E. P. Ippen, and L. C. Kimerling, "Air trench bends and splitters for dense optical integration in low index contrast," Journal of Lightwave Technology, vol. 23, pp. 2271, 2005.

  19. Shoji Akiyama, Miloš Popović, Kazumi Wada, Jürgen Michel, Lionel C. Kimerling, and Hermann A. Haus, “Air Trench Waveguide Bends for Dense Integration for Low and Middle Index Contrast Integrated Optics”, Journal of Lightwave Technology 23, 2271 (2005).

  20. M. R. Watts and H. A. Haus, “Integrated mode-evolution-based polarization rotators,'' Optics Letters, Vol. 30, No. 2, pp. 138-140 (2005).

  21. M. R. Watts, H. A. Haus, and E. P. Ippen, "Integrated mode-evolution-based polarization splitters," Optics Letters, vol. 30, pp. 967-969, 2005.

  22. L.C. Kimerling, “Silicon Microphotonics,” in Interconnect Technology and Design for Gigascale Integration, J. Davis and J.D. Miendl, Eds. (Kluwer Academic Publishers, Boston, 2003) p. 383.

  23. L.C.Kimerling, L.Dal Negro, S.Saini, Y.Yi, D.Ahn, S.Akiyama, D.Cannon, J.Liu, J.G.Sandland, D.Sparacin, J.Michel, K.Wada, M.R.Watts, “Monolithic Silicon Microphotonics” in Silicon Photonics edited by L.Pavesi, D.J. Lockwood, Springer-Verlag, Berlin, 89-119, 2004.

  24. S. Saini, J.Michel, LC Kimerling, “Index Contrast Scaling for Optical Amplifiers,” Journal of Lightwave Technology, 21 (10) 2368 (2003).

  25. L. C. Kimerling, D. Ahn, A. B. Apsel, M. Beals, D. Carothers, Y.-K. Chen, T. Conway, D. M. Gill, M. Grove, C.-Y. Hong, M. Lipson, J. Liu, J. Michel, D. Pan, S. S. Patel, A. T. Pomerene, M. Rasras, D. K. Sparacin, K.-Y. Tu, A. E. White, and C. W. Wong, “Electronic-photonic integrated circuits on the CMOS platform”, Silicon Photonics, Joel A. Kubby and Graham T. Reed, eds. Proc. of SPIE Vol. 6125, 612502 (2006).

  26. I. Dosunmu, D. D. Cannon, M. K. Emsley, L. C. Kimerling, and M. S. Unlu, "High-speed resonant cavity enhanced Ge photodetectors on reflecting Si substrates for 1550-nm operation," IEEE Photonics Technology Letters, vol. 17, pp. 175, 2005.

  27. J. Liu, J. Michel, W. Giziewicz, D. Pan, K. Wada, D.D. Cannon, S. Jongthammanurak, D.T. Danielson, L.C. Kimerling, J. Chen, F.O. Ilday, F.X. Kaertner, J. Yasaitis, “High-performance, tensile-strained Ge p-i-n photodetectors on a Si Platform” Applied Physics Letters, 87 (10), p. 103501-1-3, 2005.

  28. D.K. Sparacin, S.J. Spector, L.C. Kimerling, “Silicon Waveguide Sidewall Smoothing by Wet Chemical Oxidation” IEEE Journal of Lightwave Technology, 23 (8), p. 2455-2461 (2005).

  29. Samerkhae Jongthammanurak, Jifeng Liu, Kazumi Wada, Douglas D. Cannon , David T. Danielson, Dong Pan, Lionel C. Kimerling, and Jurgen Michel, “Large Electro-optic Effect in Tensile Strained Ge-on-Si Films”, Applied Physics Letters 89(16) 161115 (2006).

  30. Q. Xu, B. Schmidt, S. Pradhan, M. Lipson, “Micrometer-scale silicon electro-optic modulator”, Nature, 435 (7040), p. 325-327, 2005.

  31. D.K. Sparacin, J.P. Lock, C. Hong, K.K. Gleason, L.C. Kimerling, J. Michel, “Trimming of Microring Resonators Using Photo-Oxidation of a Plasma-Polymerized Organosilane Cladding Material” Optics Letters, 30 (17), p. 2251-2253, 2005.

  32. C.A Moritz, D Yeung and A Agarwal, “Simple Fit: A Framework for Analyzing Design Trade-offs in Raw Architectures”, IEEE Transacations on Parallel and Distributed Systems, 12, p.730 (2001). http://cag.csail.mit.edu/raw/documents/Moritz-SimpleFit-TPDS-2001.pdf

  33. Kimberly Kuo, Rodric Rabbah, and Saman Amarasinghe, “A Productive Programming Environment for Stream Computing,” Second Workshop on Productivity and Performance in High-End Computing, San Francisco, February 13, 2005, pp. 35-44. http://cag.lcs.mit.edu/commit/papers/05/kkuo-sdt.pdf

  34. William Thies, Michal Karczmarek, and Saman Amarasinghe, “StreamIt: A Language for Streaming Applications,” Proc. of the International Conference of Compiler Construction, 2002.

  35. Michael Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Andrew A. Lamb, Chris Leger, Jeremy Wong, Henry Hoffmann, David Maze, and Saman Amarasinghe, “A Stream Compiler for Communication-Exposed Architectures,” Proc. of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002.

  36. Andrew A. Lamb, William Thies, and Saman Amarasinghe, “Linear Analysis and Optimization of Stream Programs,” Proc. of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation, San Diego, California, June, 2003.

  37. Janis Sermulins, William Thies, Rodric Rabbah, and Saman Amarasinghe, “Cache Aware Optimization of Stream Programs,” Proc. of the 2005 Conference on Languages, Compilers, and Tools for Embedded Systems, Chicago, Illinois, June 2005.

  38. William Thies, Michal Karczmarek, Janis Sermulins, Rodric Rabbah, and Saman Amarasinghe, “Teleport Messaging for Distributed Stream Programs,” Proc. of the ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming, Chicago, Illinois, June, 2005.

  39. Matthew Drake, Henry Hoffman, Rodric Rabbah, and Saman Amarasinghe, “MPEG-2 Decoding in a Stream Programming Language,” Proc. of the 20th IEEE International Parallel and Distributed Processing Symposium, Rhodes Island, Greece, April, 2006.

  40. Lorin Hochstein, Jeff Carver, Forrest Shull, Sima Asgari, Victor Basili, Jeffrey K. Hollingsworth, and Marvin V. Zelkowitz, “Parallel Programmer Productivity: A Case Study of Novice Parallel Programmers,” Proc. of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Nov. 2005.

  41. H. Sutter and J. Larus, “Software and the Concurrency Revolution,” ACM Queue, vol. 3, no. 7, 2005, pp. 54–62.

  42. M. Creeger, “Multicore CPUs for the Masses,” ACM Queue, vol. 3, no. 7, 2005, pp. 63–64.

  43. D. Butenhof, Programming with POSIX Threads, 1997, Addison Wesley Professional.

  44. OpenMP Application Program Interface Specification, OpenMP Architecture Review Board, 1997; http://www.openmp.org/

  45. J. Dean and S. Ghemawat, “MapReduce: Simplified Data Processing on Large Clusters,” Proc. 6th Symposium on Operating System Design and Implementation (OSDI 2004), Usenix Assoc., 2004, pp. 137–150.

  46. MPI: A Message-Passing Interface Standard, Message Passing Interface Forum, 1994; http://www.mpi-forum.org/docs/mpi-11-html/mpi-report.html.

  47. Edward A. Lee, "The problem with threads," IEEE Computer , vol.39, no.5, pp. 33-42, May 2006.

  48. W. Thies, M. Karczmarek, M. Gordon, D. Maze, J. Wong, H. Ho, M. Brown, and S. Amarasinghe, “StreamIt: A Compiler for Streaming Applications,” MIT-LCS Technical Memo TM-622, Cambridge, MA. December 2001.

  49. I. Buck, 2004. Brook specification v.0.2. Tech. Rep. CSTR 2003-04 10/31/03 12/5/03, Stanford University.

  50. M.L. Chu and S. A. Mahlke, "Compiler-directed data partitioning for muiticluster processors," Proc. of the Fourth International Symposium on Code Generation and Optimization, 2006 (CGO 2006), vol., no., pp. 11 pp.-, 26-29 March 2006

  51. G. Ottoni and D. I. August, “Global Multi-Threaded Instruction Scheduling,” Proc. of the 40th International Symposium on Microarchitecture (MICRO-40), December 2007.

  52. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun, “Transactional Memory Coherence and Consistency,” Proc. of the 31st International Symposium on Computer Architecture (ISCA’04). p102, June 2004.

  53. R. Rajwar, M. Herlihy, and K. Lai, “Virtualizing Transactional Memory,” Proc. of the 32nd International Symposium on Computer Architecture (ISCA’05). pp. 494—505, June 2005.

  54. IA-64 Application Instruction Set Architecture Guide, Revision 1.0, 1999.

  55. R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth, and P. K. Rodman, “A VLIW architecture for a trace scheduling compiler,” Proc. of the Second International Conference on Architectual Support For Programming Languages and Operating Systems (ASPLOS-II). pp 180-192. 1987.

  56. J. H. Ahn, W. J. Dally, B. Khailany, U. J. Kapasi, and A. Das, “Evaluating the Imagine Stream Architecture,” Proc. of the 31st International Symposium on Computer Architecture (ISCA’04), June 2004.

  57. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese, “Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing,” Proc. of the 27th International Symposium on Computer Architecture (ISCA-2000), June 2000.

  58. K. Sankaralingam, R. Nagarajan, P. Gratz, R. Desikan, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, W. Yoder, R. McDonald, S.W. Keckler, and D.C. Burger, "The Distributed Microarchitecture of the TRIPS Prototype Processor," Proc. of the 39th International Symposium on Microarchitecture (MICRO-39), December, 2006.

  59. Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta, “The SPLASH-2 Programs: Characterization and Methodological Considerations,” Proc. of the 22nd International Symposium on Computer Architecture, pp 24-36, June 1995.

  60. Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams, and Katherine A. Yelick, “The Landscape of Parallel Computing Research: A View from Berkeley,” University of California, Berkeley, Technical Report No. UCB/EECS-2006-183, December 18, 2006.


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