UNIT-1 DEPARTMENT OF INFORMATION TECHNOLOGY::SVECW Page 28 Figure a shows atypical use of PCI in a single-processor system. The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s IO capability. Ina multiprocessor system (Figure bone or more PCI configurations maybe connected by bridges to the processor’s system bus. Again, the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly. Bus Structure PCI maybe configured as a 32- orbit bus. There are 49 mandatory signal lines for PCI which are divided into the following functional groups • System pins Include the clock and reset pins. • Address and data pins Include 32 lines that are time multiplexed for addresses and data. The other lines in this group are used to interpret and validate the signal lines that carry the addresses and data. • Interface control pinsControl the timing of transactions and provide coordination among initiators and targets. • Arbitration pins Unlike the other PCI signal lines, these are not shared lines. Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. • Error reporting pinsUsed to report parity and other errors. In addition, the PCI specification defines 51 optional signal lines, divided into the following functional groups • Interrupt pins These are provided for PCI devices that must generate requests for service. As with the arbitration pins, these are not shared lines. Rather, each PCI device has its own interrupt line or lines to an interrupt controller. • Cache support pinsThese pins are needed to support a memory on PCI that can be cached in the processor or another device. • 64-bit bus extension pins Include 32 lines that are time multiplexed for addresses and data and that are combined with the mandatory address/data lines to form a bit address/data bus. • JTAG/boundary scan pinsThese signal lines support testing procedures. PCI Commands Bus activity occurs in the form of transactions between an initiator, or master, and a target. When a bus master acquires control of the bus, it determines the type of transaction that will occur next The commands areas follows • Interrupt Acknowledge • Special Cycle • IO Read • IO Write • Memory Read • Memory Read Line • Memory Read Multiple • Memory Write • Memory Write and Invalidate • Configuration Read
