University of wisconsin madison
Evaluation of the Translation Modeling and Strategy
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- Figure 3.10 BBT and SBT overhead via simulation
- Figure 3.11 VM performance trend versus hot threshold settings
- Table 3.1 Benchmark Characterization: miss events per million x86 instructions
- VM: M BBT VM: M HST VM: M L2
- Average 1503.0 33.5 7409.0 365.7
3.4Evaluation of the Translation Modeling and StrategyThe analytical model that estimates DBT translation overhead (Equation 1) is evaluated by comparing its projections with performance simulations. The simulations are conducted for the baseline VM system running the Windows application traces. Figure 3.3 shows the runtime overhead for both the BBT and the SBT relative to the entire execution time. Clearly, BBT translation overhead is more critical and is measured at 9.6%, close to the 10% prediction based on the analytical model. The SBT hotspot optimization overhead is also fairly significant and is measured at 3.4%, close to the 3% projected by the equation. 
Figure 3.10 BBT and SBT overhead via simulation Furthermore, the BBT translation must be performed on the critical execution path because in our VM system there is no other way to emulate a piece of code that is executed for the first time. On the other hand, the SBT optimization is relatively more flexible because the BBT translation is still available. This flexibility leads to more opportunities to hide SBT optimization overhead. Figure 3.3 corroborates the observation derived from Figure 3.1 that runtime overhead affects the VM startup performance significantly; it can not be simply assumed to be negligible at least for the applications that we enumerated in Chapter 1. 
Figure 3.11 VM performance trend versus hot threshold settings The analytical model that estimates the appropriate thresholds (Equation 2) for triggering more advanced translation stages is evaluated by observing how the VM system performance varies as the hot threshold changes around the ranges predicted by the equation. Thresholds too low will cause excessive translation overhead while thresholds too high reduce the hotspot code coverage and thus the optimization benefits. Typically, as the hot threshold increases, the hotspot size decreases more quickly than the hotspot coverage. Figure 3.4 plots the VM IPC performance versus hot threshold trend for each benchmark traces from the WinStone2004. As the hot threshold increases from 2K to the optimal point (8K, determined by Equation 2), the VM performance clearly increases. After the optimal point, the VM performance gradually decreases. Figure 3.4 verifies that the analytical model calculates a fairly balanced hot threshold based on averages for the whole benchmark suite. However, the best performance point for each specific benchmark is different. Perhaps, this suggests an adaptive threshold for each application or even each program phase for optimal performance and efficiency. An assumption in the previous discussion is that the different memory hierarchy behavior (VM versus baseline superscalar) causes only second-order performance effects. This assumption is the basis for the simple VM system analytical model, which only models translation behavior. Although this assumption matches common sense, supportive data and analysis will now be given to validate this assumption. Compared with a conventional superscalar processor, the co-designed VM system has three major performance implications.
Similar to the notation for translation modeling, ML2 and Mmem are the number of instruction fetch misses to L2 cache and main memory respectively. ΔL2 and Δmem represent the miss penalty for a miss to L2 cache and main memory accordingly. For a specific memory hierarchy level, the instruction miss penalty tends to be nearly constant [73] and is closely related to the access latency for the memory level that services the miss. Typically, the access latency is easily determined via simulations. We collect data to compare the last two implications and determine if memory behavior difference causes only second-order effects. Table 1 shows miss rates for the listed benchmarks running 100M x86-instruction traces. The simulations are configured similar to Figure 3.1 and 3.2. Table 3.1 Benchmark Characterization: miss events per million x86 instructions
Two factors affect the VM system memory hierarchy behavior, (1) code straightening via hot superblock formation for hotspot optimization, (2) code expansion and translator footprint. Because we translate x86 instructions into a RISC-style ISA, there is some code expansion. In general, the 16/32b fusible ISA binary has a 30~40% code expansion over the 32-bit x86 binaries. Table 3.1 shows that the VM system causes more instruction cache misses to the L2 cache, 0.0013 more misses per x86 instruction. Assuming a typical L2 cache latency of 10-cycle, the extra instruction cache misses lead to a 0.013 CPI adder for the VM system. In real processors, some of the L1 misses can be tolerated. The latency to the DRAM main memory is much longer, well over 100-cycles. The VM system causes 0.000032 more misses to memory per x86 instruction. Therefore, assuming a 200-cycle memory latency, the extra misses to main memory will cause another 0.0064 CPI adder to the VM system CPI. In summary, the different memory hierarchy behavior will cause an overall 0.02 CPI adder to the VM system. Now consider the translation overhead, there are two sources of translation overhead, the BBT overhead and the SBT overhead, It is clear from the above data and analysis that the DBT translation overhead is an order of magnitude higher than the extra memory miss-penalty. This analysis backs up the assumption that the different memory hierarchy behavior causes only second-order performance impact.
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. On average, about 1.5 out of every 1000 x86 instructions executed need to be translated by BBT in the tested traces. Assuming a typical BBT translation overhead of 100-cycles per x86 instruction, the CPI adder due to BBT translation is 0.15. Table 3.1 shows about 33.52 instructions are identified as hotspot per million dynamic x86 instructions. Assuming a 1500 cycle SBT overhead per x86 instruction in the VM system, the data suggests that the SBT overhead leads to another CPI adder of about 0.05 for the VM model.