Abstract The "Smart Walker"



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Sound Localization and Fall Detection

with Four Microphone Arrays
Abstract

The “Smart Walker” is an advanced walker for the elderly, capable of obstacle avoidance and navigation, vital sign acquisition, and fall detection. Through the use of four linear microphone arrays, sound can be detected and localized, in order to determine the direction in which a user of the walker may have fallen, or is in need of assistance. Due to the nature of sound, the planar waves from a specific direction around the walker will arrive at each microphone at different intervals of time after the initial instance of sound. Using an MSP430 microcontroller to store the samples from each microphone and pre-calculating these delays, sound from around the walker can be separated into individual channels, which represent Azimuthal directions from 0 to 360 degrees.


Nomenclature

NSF- National Science Foundation

RIT - Rochester Institute of Technology

SBC - Single Board Computer

SNR - Signal-to-Noise Ratio

UGALS - User-Guided Assistive Listening System

USB - Universal Serial Bus

Concept design

Four linear arrays of 8 microphones each will be utilized. Although it is possible to detect a fall with just a 2-microphone linear arrangement, increasing the number will drastically decrease the probability of error. As the result of previous research and development performed at RIT for the NSF project entitled UGALS [1], a 2-dimensional array has been created and tested to provide accurate sound localization with a SNR of approximately 25 dB. This array consists of 4 separate PCBs, with 64 MEMS based Analog Devices ADMP441 microphones on each (8 x 8 configuration), for a total of 256 microphones. Using a similar configuration as one of these boards, we can create a 8-microphone linear array by “slicing” one row of the 8 x 8 arrangement. An array will be located on the front bar, both sides, and the rear bar of the walker, for a coverage of 360 degrees surrounding the walker. Instead of the ZynqTM-7000 FPGA used in the NFS UGALS microphone array [1], an MSP430F5507 microcontroller will be programmed to capture and store all samples from different location channels, representing degrees of rotation around the walker.



Processor Clock calculations

The predetermined sampling frequency for the microphones was initially 48 kHz, or twice the highest frequency of human hearing, 24 kHz. However, this was based on the high fidelity, live audio streaming necessary for the applications of the NFS UGALS project [1]. According to the data sheet for the ADMP441 microphones [2], the word select (WS) clock is configured as the sampling frequency, while the bit clock (SCK) is set to be 64 times the sampling frequency, or 3.072 MHz. Since the frequency range for human speech peaks around 5 kHz, the sampling frequency can be lowered to 10 kHz (the Nyquist rate for 5kHz). The SCK signal is then lowered to 0.64 MHz and if the microcontroller main clock runs at 24 Mhz (max of 25 MHz according to p. 46 in the data sheet for MSP430F550x, MSP430F5510 microcontrollers [3]), there are approximately 30 clock cycles (TCLK) per one clock cycle of the 0.64 MHz clock. We can round the values for the SCK and WS according to the dividers available for Timer A in the MSP430, resulting in a 9.37 kHz sampling frequency for the WS and a 0.6 MHz clock for SCK.


Figure 1. Processing Time for CPU (MSP430F5507 microcontroller)
According to Figure 1, after acquiring a 24 bit sample from the microphones, there is approximately 240 TCLK cycles available to process. The first bit when the WS goes low or high is ignored because of a possible timing delay. Therefore the processing begins on the 26 bit. If we choose to process during sampling, there are approximately 40 TCLK cycles per sample bit. In order to store samples, it requires 2 instructions, which is about 10 clock cycles (on average 5 cycles per instruction). Therefore there are about 30 cycles leftover to process during each sampled bit and 24 sampled bits, which results in 720 cycles per sample. This yields a total of 960 cycles available during each half of the WS clock.
SAMPLE INDEX CALCULATIONS

There will be a total of 8 microphones in each array, with a spacing of 3 cm (0.03 m) between each. Since sound waves propagate as parallel lines, imagine a sound source reaching each successive microphone at different times, as seen in Figure 2 by the angled blue lines. The time delay between each microphone is represented by tD. The distance D represents the distance the sound wave travels during the delay between M8 and M7. It can be calculated as D equals tD times CS, where CS represents the speed of sound (340.29 m/s). With this distance and the spacing between M7 and M8, the Azimuthal angle can be calculated using the law of cosines.

Figure 2. Planar waves of sound source entering array at angel θ from M8 side

cos(θ) = D / 3 cm

θ = cos-1(D / 0.03 m) = cos-1(tD * CS / 0.03 m)

θ = cos-1(tD * 340.29 / 0.03)

By presetting these delay times, we can "steer" the array towards any direction we want. Since the data from all microphones is continuously being stored, these delay times correspond to which sample from this data is taken to be used in the delay sum calculation. If each microphone's data is stored in a separate array (successive address locations), the samples corresponding to specific delays can be extracted, summed, and stored into a new array (new address locations). Each sample is then added collectively and stored as one sample for this delay, or Azimuthal direction.


According to the time delays for specific angular directions around the walker, indices corresponding to samples in storage can be calculated. These sample indices are used to determine which sample for each successive microphone needs to be extracted from memory. For example, sound entering the array at an angle of 90 degrees (broadside) arrives at all microphones at the same instance in time. This means that first sample in storage for all microphones is used in order to determine the averaged sample for the 90 degree direction. The indices would look something like [0,0,0,0,0,0,0,0], where 0 corresponds to the first sample in storage. For sound entering the array at 0 degrees from either side (indices would for sound entering microphone 1 first would be opposite of that for sound entering microphone 8 first), the indices would change. If sound arrived at microphone 1 first, the first sample in storage is valid for microphone 1. However, the sound would arrive at microphone 2 a period of time equal 88.16 microseconds later (determined by law of cosines mentioned above for 0 degree angle). Therefore, the index corresponding to this delay would be 88.16 microseconds times 9.37 kHz, or 0.82 (rounded to the nearest integer). Then for microphone 3, the sound would arrive another 88.16 microseconds later, resulting in an index of 1.64, or 2 when rounded. The resulting indices for all microphones would look like [0,1,2,2,3,4,5,6]. This process can be completed for all angles of direction around the walker.
MAXIMUM NUMBER OF SAMPLES

In order to calculate the maximum number of samples need for each microphone, we must look at the case in which sound enters the array broadside, or at 0/180 degrees (Figure 3). Since the speed of sound is 340.29 m/s and the distance between each microphone is 3 cm, we can calculate the time it takes sound waves to propagate from one microphone to the next by dividing. Therefore, our delay time for each successive microphone is 3 cm divided by 340.29 m/s, which equals 88.16 microseconds.

Figure 3. Sound entering array at 0 degrees (max time delay)
Now, we can use our sample frequency of 9.37 kHz to calculate how many samples we need in order to pull a valid sample for a sound wave propagating from microphone 8 to microphone 1. Our first sample for each microphone, would be when the sound wave first hits microphone 8. Since the sound has not yet reached all other microphones, the samples for those microphones would be invalid. After the associated delay of 88.16 microseconds, the sound wave would reach microphone 7, and the sample associated with this delay would now be the valid sample for microphone 7, however all of microphone samples at this point would be invalid. Microphone 8’s valid sample is the first one, microphone 7’s valid sample is the one occurring 88.16 microseconds after the initial sample, and all other microphones do not have a valid sample yet. This method cascades down the array as seen in Figure 4.

Figure 4. Delay of 88.16 microseconds from M8 to M1


Since the sample frequency determines how often we take a sample, we can multiply this by the total delay at microphone 1 to give us what sample is valid at microphone 1, or the minimum number of samples needed to achieve valid samples for all microphones. The number of samples needed is 9.37 kHz times 617.12 microseconds, equaling approximately 6 samples. For a sample frequency of 48 kHz, as proposed initially, the number of samples needed for a zero degree channel is 30.
DAUGHTERBOARD - 4 ARRAYS TO 1 CENTRAL CONTROLLER

In order to communicate and synchronize between the four microphone arrays located on all sides of the walker, a central microcontroller is needed. This is located on the daughterboard which is placed within the basket of the walker. The daughterboard serves a few purposes:

Combines all microphone array outputs into a single USB connection for the SBC.

Regulates 12 volt battery source to a stable 3.3 volt source used for all components on the microphone arrays with the MIC2920 Voltage Regulator [4].

Microcontroller communicates with all arrays in order to send serial data to SBC.
We can utilize the Slave In Master Out and Slave Out Master In ports on the MSP430 in order to communicate between the daughterboard and all microphone arrays. See Figure 5 below for wiring diagram.
Figure 5. SOMI/SIMO Wiring Diagram

ARRAY and daughterboard pcb

Due to the protocol used for serial data output of the ADMP441 microphones (I2S), as stated on p. 8-9 in the ADMP441 specification sheet [2], a pair of microphones can be connected on the same output line, and configured to operate as a stereo output. For the applications used in the Smart Walker, this configuration can be utilized for all 8 microphones, creating 4 serial data outputs. Instead of a stereo image, the microphones will simply be enable at different halves of the sampling frequency, ie. Microphones 1, 3, 5 and 7 will be sampled while the WS is high, and microphones 2, 4, 6, and 8 will be sampled while it is low. Along with decoupling capacitors, 100 k pull-down resistors and isolation resistors, this 8 microphone configuration can be excerpted from the 64 microphone configuration found in the P1095 MSD project [1]. The PCB footprint for the ADMP441 can be found in the specification sheet [2].


Due to possible time delays that can arise from different trace lengths for clock signals, all clock traces are made equal in length, as well as all serial data outputs. Although the delay is minute, it is in good practice to set all lengths equal. In order to achieve the necessary system clock of 24 MHz, one of two options can be used: The internal system clock of the microcontroller can be set to 24 MHz, or an external oscillator can be used. With an external oscillator, the clock signal is more precise than that of the internal system clock. Therefore a 24 MHz oscillator is utilized and the footprint can be found in XPress0 HCMOS Oscillator specification sheet [5].
Also stated within the P1095 MSD project [1], it is necessary to include signal buffers for the WS, SCK, and serial data outputs for all microphones. This is due to the distances each signal must travel to reach the microcontroller. As for the Smart Walker application, these buffers may not be necessary, but are included to negate any possible loss of clock or data signals within the board. The PCB layout for one microphone array can be seen in Figure 6 - Figure 8 below and the layout for the daughterboard in Figure 9.

Figure 6. Microphones 1 and 2 (MK1 and MK2, respectively)

Figure 7. U8 - Microcontroller, U9 - Oscillator, J1 - 4 pin connector for SOMI, SIMO and power supply connections, J2 - JTAG Connector, and other necessary components.

Figure 8. WS buffer for microphone array. U5 - U7 are the Texas Instruments SN74LVC1G125 single buffer [6].

Figure 9. Daughterboard PCB layout.
In Figure 9, the connectors J1 - J4 are the 4 pin connections coming from the 4 microphone arrays. The component U1 is the MIC2920 voltage regulator and component U2 is the MSP430 microcontroller. Connector J5 is for the JTAG connection used in programming and the connector J6 is the USB output for the SBC.

References

[1] Amuso, Vincent J., PhD and Borkholder, David A., PhD. National Science Foundation Project #31095, P1095 User-Guided Assistive Listening System.


[2] Analog Devices ADMP441. “Omnidirectional Microphone with Bottom Port and I2S Digital Output.” Rev. B 2011-2012 Analog Devices, Inc. Norwood, MA.
[3] Texas Instruments, MSP430F550x, MSP430F5510. “Mixed Signal Microcontroller.” 2009-2012 Texas Instruments, Inc.
[4] MICREL MIC2920A/29201/29202/29204. “400mA Low-Dropout Voltage Regulator.” San Jose, CA. February 2005.
[5] FOX FXO-HC53 Series. “XPress0 HCMOS 5 x 3.2mm 3.3V Oscillator.” 2008. Fort Myers, Florida.
[6] Texas Instruments, SN75LVC1G125. “Single Bus Buffer Gate With 3-State Output.” Rev. November 2012. Texas Instruments, Inc.
Acknowledgments

[1] Patru, Dorin X., PhD. Associate Professor, Rochester Institute of Technology.





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