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This chapter documents UND’s algorithm and simulation efforts regarding frequency-based load shedding in the UWM microgrid. An important feature of the UWM controller is that the line frequency droops when there is power drawn by system loads exceeds the requested power set point. This frequency droop can be seen as a symptom of system stress and one way of quickly addressing this issue is to drop resistive loads. Odyssian’s e-board load units carried out the load shedding function. This section describes the algorithms recommended for Odyssian’s e-board units.
6.1 Line Frequency Estimator Design and Evaluation
Load-shedding algorithm drop load when the frequency droops below a specified threshold. The load shedding algorithms used by Odyssian’s e-board, would therefore need to estimate the voltage line’s frequency with sufficient accuracy to ensure fast disconnection when the frequency droops. The original frequency estimator proposed by Odyssian was based on counting zero-crossings over a specified time interval. This approach generated estimates that had a precision of 1.0 Hz every 0.3 seconds.
An example of the estimated frequency is shown in figure 26. This simulation was generated for the microgrid simulation model used in testing the CERTS controller on a microsource. To generate frequency estimates with greater precision would require a greater interval between estimates. This level of estimation performance is inadequate for load shedding. 
Figure 26: Estimation performance of Odyssian’s original zero-crossing frequency estimator
Figure 27: Simulink model of phase-locked loop estimator
An alternative frequency estimator was designed using a phase-locked loop (PLL). In this estimator, the input waveform is mixed with a 60 Hz sinusoid and then run through a low pass filter. The output of this filter is used to change the frequency of a voltage-controlled oscillator (VCO) generating the mixing sinusoid. The output of the filter represents the change in frequency from the 60 Hz reference sinusoid. This method provides an extremely fast and accurate estimate of the input signal’s frequency. A simulink block diagram for the PLL frequency estimator is shown in figure 27.
The simulink model was constructed as a digital model assuming a sampling time of 10 msec. The key components in the filter are the biquad filter and the modulo digital integrator. The “modulo” nature of the integrator prevents integrator overflows that can reduce accuracy. The Biquad filter is an elliptical low pass digital filter with a 100 Hz sampling frequency, a 5 Hz cutoff frequency, and a 20 Hz stop band frequency with 40 dB attenuation. The filter was implemented as a two-stage biquad structure in direct form II. A block diagram for this filter is shown below in figure 28.
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