AMERICAN UNIVERSITY OF SCIENCE & TECHNOLOGY Faculty of Engineering
Department of Biomedical Engineering
Computer Organization and Microprocessor
CCE320
Assignment 1
Intel Celeron Processor
Internal Architecture
The Intel Celeron was launched in 1999 as an alternative of the Pentium III chip. It is based on the P6 Dynamic Micro-architecture.P6 architecture has a 10-stage pipeline and an x86 decoder that translates x86 CISC instructions in internal RISC code. Intel Celeron has 2 cache latches each with 32KB and 128Kb, 66 Mhz front-bus speed with the cores running at 100Mhz front-bus speed, socket 370 interface, clock speed of 266 Mhz, 64 GB memory that is addressed by 36-bit address space, and x-86-64 CPU.
How it works
Eight 128-bit registers are used in the Streaming SIMD Extension (SSE) instruction set to execute packed single floating-point operands. A single register is filled with many different values using packed operands. Four 32-bit segments make up the 128-bit register in this instance. To mask/unmask the exception handling, set the rounding mode, set the flush-to-zero mode, and inspect status flags, a new MXCSR register was implemented. Arithmetic, logical, comparison, shuffle, conversion, data movement, state management, additional SIMD integer, and cacheability control instructions are among the nine different types of SSE instructions. The extra 64-bit MMX registers are used by the additional integer instructions.
Von Neuman or Harvard Architecture
Intel Celeron processor uses Von neuman architecture since there is noseparation between between the data and the code memory.
References
The Intel Celeron Processor. (n.d.). Retrieved February 27, 2023, from https://ininet.org/the-intel-celeron-processor.html
GeeksforGeeks. (2022, December 20). Computer Organization: Von Neumann architecture. GeeksforGeeks. Retrieved February 27, 2023, from https://www.geeksforgeeks.org/computer-organization-von-neumann-architecture/
