An fpga implementation of the Smooth Particle Mesh Ewald Reciprocal Sum Compute Engine (rsce)

Chapter 5 7.Verification and Simulation Environment

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Chapter 5

7.Verification and Simulation Environment

This chapter details the effort of verifying the RSCE design and it also describes the SystemC simulation environment that allows studies of the RSCE calculation precision requirement. Furthermore, it also presents the result of the demo MD simulations when the RSCE is used with NAMD2 software.

7.1.Verification of the RSCE

This section discusses the RSCE design verification effort. It first describes the implementation of the RSCE SystemC model, then it describes the RSCE verification testbench, and lastly, it explains the program flow of a verification testcase.

7.1.1.RSCE SystemC Model

A SystemC model is developed to calculate the SPME reciprocal energy and forces with either fixed-point arithmetic or double precision arithmetic. The ability to use different arithmetic and precision is achieved by using the template class and functions of the C++ programming language. With the template classes and functions, the same model can be used for different data types. Furthermore, with the template specialization feature, the C++ and the SystemC functions can be mixed together to ease the implementation.
During the development of the SystemC simulation model, the golden SPME implementation is used as a reference to ensure the correctness of the simulation model in all calculation steps. Furthermore, the SystemC model is developed to model the hardware architecture closely. The structure of the SystemC RSCE model is shown in Figure 58. As shown in the figure, the SystemC model consists of the same design blocks (BCC, MC, 3D-FFT, EC, and FC) as the hardware implementation. In this way, design or architectural issues can be investigated before the actual RTL design is implemented. Furthermore, this enhances the verification capability of the model and eases the integration of the SystemC model into the verification testbench.
Separate from the RSCE SystemC model, another SystemC model is also developed to represent the host that communicates with the RSCE to carry a single-timestep MD simulation. The host SystemC model is responsible for filling the PIM memory with the shifted and scaled fractional coordinates and the charge of the particles, the BLM memory with the B-Spline coefficients, derivatives and slope of the derivatives at the predefined lookup points, and the ETM memory with the energy term of the grid points. Once it finishes filling the memory arrays, it calls the RSCE functions to perform the timestep computation either with the user-specified fixed-point arithmetic or with the double precision floating-point arithmetic. The host SystemC model (HOST) is shown on the left side of Figure 58. As illustrated in the figure, the host SystemC instantiates an eterm calculator (ETMC) and a B-Spline Coefficient Calculator (BCC) which are responsible for filling the ETM and the BLM lookup memories respectively.

Figure 58 - SystemC RSCE Model

7.1.2.Self-Checking Design Verification Testbench

This section describes the verification environment for the RSCE development. The testbench, the memory models and the bus functional model (BFM) are implemented in SystemC. As shown in Figure 59, the verification environment consists of the following components:

  1. A testcase that takes a protein data bank (PDB) file as input and provides various configurations setting (e.g. interpolation order, grid size, etc.) and particle information to the RSCE testbench (RSCE_TB).

  2. The RSCE testbench (RSCE_TB) that instantiates the BFM (opbBfm), the RTL design (through a SystemC wrapper), the memory models, the checker and the RSCE behavioral model.

  3. An OPB bus functional model (opbBfm) that models the MicroBlaze OPB interface that sends the instructions to both the RSCE RTL and the RSCE behavioral model.

  4. Five memory models that model the ZBT memories on board. The memory models also act as checkers to monitor and verify the memory accesses from both the RSCE RTL and the RSCE behavioral model.

  5. A checker that verifies that the calculated energy and forces from the RSCE RTL are the same as the results from the behavioral model.

Figure 59 - SystemC RSCE Testbench

7.1.3.Verification Testcase Flow

A verification testcase starts with the testcase reading from a test-specific PDB file for a molecular or atomic system. From the PDB file, the testcase obtains the simulation box dimension and the Cartesian coordinates and charge of all particles. On the other hand, the interpolation order and the grid size are set according to the purpose of the test.
After all test information is gathered, the testcase calls the host SystemC model to perform calculations and fill the BLM, the ETM, and the PIM SystemC memory models through a backdoor mechanism. Furthermore, the entries that constitute the charge grid in the QMMR and the QMMI memory are cleared to zero.
After all the memories are initialized, a number of OPB packets can be constructed and sent to the RSCE. These OPB packets represent transactions to program the RSCE registers and configure the RSCE to perform the reciprocal sum calculation for one timestep. The register programming sets up the interpolation order, the grid size, and the number of particles in the simulation. At the same time, an equivalent microprocessor packet (upPkt) is sent to the RSCE behavioral model to configure it for the same reciprocal sum calculation.
At this point, the computation starts and every memory transaction from the RSCE RTL is logged and checked against the behavioral model during the simulation. The testcase keeps polling the RSCE status register to check if the energy calculation is complete and if so, it then reads and checks the reciprocal energy calculated by the RSCE RTL by comparing it against energy calculated by the behavior model. On the other hand, since the reciprocal forces are written to the lower half of the PIM memory, they should be automatically checked.
The same test flow can be used with different interpolation orders, different grid sizes, and different input PDB files and the self-checking verification testbench should still be able to verify the functional correctness of the RSCE RTL without any modification.

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