SymTA/S is a tool for the development and verification of embedded multiprocessor real-time systems. The existing technology is mainly suitable for event or time-driven systems with message passing as the main task interaction. The tool shall be extended to cover the timing implications of multicore processors, or multiprocessor-systems-on-chip.
In several previous projects (funded by german DFG, “Sureal”, funded by german BMBF, ARTIST2, and others), the compositional analysis approach has been transferred into a tool framework which is now also commercially available. The available modelling options capture typical problems in todays automotive systems (CAN bus utilization, end-to-end deadlines,…). This addresses a growing need for formal methods in the industry. The topics currently under research (see below) address future problems which can be expected to become of increasing industrial interest in the future.
The research version of the tool framework is currently being developed into several new directions: Modeling of shared resources for multiprocessor-system-on-chips (see ArtistDesign Activity 6.2: Platform and MpSoC Analysis), the modelling of hierarchical event models (in the scope of the COMBEST project), the demonstrator platform for adaptive systems (see ArtistDesign 7.1: Design for Adaptivity), and the reliability analysis (as presented in Section 3.1 Technical Achievements of the Industry-driven integrtation activity 7.3). Besides the extension of the applicability into new domains driven by industrial applications, a major focus within ArtistDesign is the synergetic coupling of tools, as well as the corresponding development of models.
TU Braunschweig investigates synergies in the coupling of methods and implements prototypical implementations of the research results.
Symtavision is the commercial co-developer of the tool framework. A focus within ArtistDesign is the coupling of with other industrially available tools (such as aiT).
Collaboration on the coupling of MPA and SymTA/S with respect to modelling of hierarchical event models.
The aiT tool supplies task timing models, which are required for system level analysis.
Simon Schliecker, Jonas Rox, Mircea Negrean, Kai Richter, Marek Jersak and Rolf Ernst, "System Level Performance Analysis for Real-Time Automotive Multi-Core and Network Architectures,"Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, No. 7, pp. 979-992, July 2009.
Simon Perathoner, Ernesto Wandeler, Lothar Thiele, Arne Hamann, Simon Schliecker, Rafik Henia, Razvan Racu, Rolf Ernst and Michael González Harbour, "Influence of different abstractions on the performance analysis of distributed hard real-time systems,"Journal Design Automation for Embedded Systems, vol. 13, No. 1, pp. 27-49, June 2009
Mircea Negrean, Simon Schliecker and Rolf Ernst, "Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources," in Proc. of Design, Automation, and Test in Europe (DATE), (Nice, France), April 2009
COSI (Communication Synthesis Infrastructure) is a software framework for interconnect infrastructure analysis and synthesis
The framework allows developing specialized flows and tools for communication synthesis as exemplified by the release of COSI-NOC (Communication Synthesis Infrastructure for Network-on-Chips), a software toolkit for the automatic synthesis of synchronous networks-on-chip based on the platform-based design paradigm, and by COSI-BAD, for building automation design.
Figure 1. The COSI Platform-Based Design-like structure
Figure 2. How the COSI framework has been used to generate specific synthesis tools.
We continue to work towards expanding COSI capabilities, including better models for router delays, bus models, and support for the generation of synthesizable RTL description of the synthesized on-chip interconnection network. In this domain, we are integrating Metro with COSI. Meanwhile, we also plan to continue our work on the extension of the communication synthesis approach to the design of large-scale network for distributed embedded systems such as those that can be found in smart buildings and to airplane power distribution.
Trento Setting the directions of the framework. Methodology and theory. Integrating COSI with Metro.
UC Berkeley Tool development and application to Network on Chip and intelligent buildings
Columbia Participation in the development of the methodology.
Application to intelligent buildings and avionics.
[PCSV08] A. Pinto, L. Carloni and A. Sangiovanni Vincentelli, COSI: A Framework for the Design of Interconnection Networks, IEEE Design and Test of Computers, vol. 25, n. 5, Sept-Oct. 2008, pp. 402-415.
[PCVS09] A. Pinto, L.P. Carloni, and A. Sangiovanni-Vincentelli. "A Methodology for Constraint-Driven Synthesis of On-Chip Communications," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 3, March 2009.
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4.7.3Metropolis and Metro II
System-Level Design (SLD) means many different things to many different people. In our view, system-level design is about the design of a whole that consists of several components where specifications are given in terms of functionality with additional:
constraints on the properties the design has to satisfy and on the components that are available for implementation and
objective functions that express the desirable features of the design when completed.
This definition is general since it relates to many different application domains, from semiconductors to systems such as cars and airplanes, buildings, telecommunication and biological systems. To deal with system-level problems, our view is that the issue to address is not developing new tools, albeit they are essential to advance the state of the art in design, rather it is the understanding of the principles of system design, the necessary change to design methodologies and the dynamics of the supply chain. Developing this understanding is necessary to define a sound approach to the needs of the system and component industry as they try to serve their customers better, to develop their products faster and with higher quality.
This contribution was about principles and how a unified methodology together with a supporting software framework, as challenging as it may seem, can be developed to bring the embedded electronics industry to a new level of efficiency. To demonstrate this view, we developed over the years Metropolis, a software framework supporting the methodology and Metro II, a second generation framework built to alleviate the problems we encountered when applying Metropolis to industrial test cases.
We are integrating this framework with the COSI framework to provide a full communication requirement capture, synthesis, verification and implementation. In parallel, we are interfacing Ptolemy to Metro II to offer a new way of entering designs using the graphical UI of Ptolemy II. In addition, TRENTO in collaboration with VERIMAG has worked on the integration of BIP functional models into the MetroII environment, in order to study the performance of the system when mapped onto different architecture platforms. The tool integration enriches the capabilities of the two tools and preserves the structure and the semantics of the original model. The method has been tested on a distributed sorting algorithm case study.
Tool development, application of the framework to a UMTS case study.
Interface with COSI and application to smart buildings and avionics.
Industrial development of the ideas put forth by the frameworks
Application to SoC design and development of architectural models
[DSDP09] D. Densmore, A. Simalatsar, A. Davare, R. Passerone, and A. Sangiovanni-Vincentelli. “UMTS MPSoC design evaluation using a system level design framework”. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE09), Nice, France, April 20-24, 2009.
[BDDD09] F. Balarin, A. Davare, M. D'Angelo, D. Densmore, T. Meyerowitz, R. Passerone, A. Pinto, A. Sangiovanni-Vincentelli, A. Simalatsar, Y. Watanabe, G. Yang and Q. Zhu. “Platform-Based Design and Frameworks: Metropolis and Metro II”. In Model-Based Design for Embedded Systems, chapter 10, page 259. CRC Press, Taylor and Francis Group, Boca Raton, London, New York, November 2009.
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Reported on integration between BIP and MetroII
4.7.4Parametric Schedulability Analysis
Parametric Schedulability Analysis (PSA) performs parametric analysis on a real time system model. A real time system consists of tasks with deadlines. Each task can have different activation patterns (periodic, aperiodic) and different design parameters such as computation time and the offset in the task activation pattern.
In the design phase of real time systems, every design variable must be assigned a value that would ensure the correct function of the system, achieved when none of the tasks misses its deadline. The classical real-time scheduling theory and available tools so far only provide designers with analysis of the system for a speciﬁc choice of the parameters. And most of the time it does not offer ﬂexibility in the choice of the activation patterns for each tasks.
In contrast to the state of the art, this tool enables users to specify their models with full parametric views of the design variables. The tool then performs parametric schedulability analysis of the system and provides the user with information of the region of the parameter values that will guarantee the system to be schedulable. This information can then be used as a guide in deciding the optimum design variable values.
Automatic parameter constraints derivation for periodic tasks with offsets using symbolic model checking
For a system with all periodic tasks with offsets and fixed priority with preemptive scheduling policy, the modelling of the system has been taken care of. The admitted design variables are computation time, periods, offsets, and deadlines. Given the system specification below:
the upper bound and lower bound for the parameter values, and
the valuation for other fixed design variables,
the tool performs parameter analysis on the system and provides the region of feasible values for the parameters in the form of constraints.
Partial analysis of the system, i.e., only checking the feasibility of some higher priority tasks, is also allowed. This feature is the implementation for the work in [RTSS08].
UPPAAL trace sampling
The tool utilizes a parameter space sampling technique to obtain regions in shorter time. Users can set the granularity of the sampling by specifying the number of datapoints to be searched in each parameter space. The tool performs sensitivity analysis on the datasample points and collects the resulting region. This approach is suitable for larger systems or cases with many parameters where full symbolic exploration of the parameter space is expensive. This approach could be done independently or in combination with the full symbolic analysis of the parametric system.
TRENTO and ETHZ have worked on the parametric analysis and validation of embedded systems specified in real-time calculus. For this, the partners have developed an integration flow between Modular Performance Analysis (MPA) developed at ETHZ and the Parametric Schedulability Analysis (PSA) developed at TRENTO. The tool allows the feasibility of a system to be studied in a range of parameters. The method has been tested on simple cases, and on a more advanced system that uses state based components which are difficult to model in MPA.
Trento Tool development, case studies
ETHZ Integration with MPA
[RTSS08] Alessandro Cimatti, Luigi Palopoli, Yusi Ramadian, Symbolic Computation of Schedulability Regions Using Parametric Timed Automata, In Proceedings of IEEE Real-Time Systems Symposium'2008. pp.80~89
[SRPL11] Alena Simalatsar, Yusi Ramadian, Roberto Passerone, Kai Lampka, Simon Perathoner and Lothar Thiele. Enabling Parametric Feasibility Analysis in Real-time Calculus Driven Performance Evaluation. In Proceedings of the International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES11), Taipei, Taiwan, October 9-14, 2011.
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This is new material, not reported in the Y3 deliverable
5.Assessment of the Workpackage at the end of Y4
The ArtistDesign Network of Excellence is a significant evolutionary step for integrating the leading embedded systems design research teams in Europe.
The overall assessment for the WP at the end of ArtistDesign of the NoE (Jan 2008–Mar 2012) is very positive - both in terms of impact on the overall structuring and lasting integration within the consortium and more generally within the area in Europe.
The ArtistDesign clusters have been actively pursuing operational integration through joint meetings, staff mobility, and shared platforms and tools.
The level of activity shows that the Cluster / Activity structure and research topics defined for ArtistDesign make sense, and are viable vehicles for integrating the area. In operational terms, they generate sufficient interest for the partners and individual researchers to participate actively in the joint meetings, to exchange personnel, and to orient the tools and platforms developed to make sense within this structure.
There is clearly a growing level of maturity for tools and platforms – and the partner teams are actively pursuing a policy of implementing tools, demontrators, and in many cases their accompanying methodologies.
Nonetheless, it is important to remember that these are tools and platforms for research. The aim is not necessarily always for these to lead to commercially viable tools and start-up companies. In general, they are the concrete realisation of the state-of-the-research, allowing to explore possibilities for future research and later tools (some of which may in turn lead to commercially viable products).
In particular, in Y4 we have had 52 joint technical meetings (public and private), covering a broad spectrum of topics and bringing together a wide audience.
The NoE has facilitated the mobility of 58 researchers in Year 4. This is widely considered to be the best way to integrated research teams, through the phyical transfer of persons and competencies. They lead to lasting collaboration and synergy.
The level of effort has been maintained. We currently have 50 tools and platforms developed in collaboration with ArtistDesign, covering the technical domains of the NoE.
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