Interconnect Serializer-Deserializer Jitter Reduction Hardware for Autonomic Computing

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Title: Interconnect Serializer-Deserializer Jitter Reduction Hardware for Autonomic Computing
Principal researchers: Michael L. Bushnell (Rutgers), Tapan J. Chakraborty (Bell Labs.)

Status: Ongoing

In recent multi-core microprocessor and data center computers, interconnect scaling has emerged as a critical issue. At present, parallel 32 and 64 bit busses are being replaced with serializer-deserializer (SERDES) busses, where one pair of differential wires carries the bus between two chips. The issue the forced this change was the problem of skewing of data transitions on the bus. In going from chip to chip, not all of the data or address lines on the bus would change simultaneously, due to electrical crosstalk, electro-magnetic interference, and variability in transistors within a single chip. The result was data errors in the bus. Instead, with SERDES, we serialize 10 bits of parallel data, and shift them out of the transmitter chip at a much higher clock rate than the normal system clock. The clock, in fact, is embedded in the data. The receiver chip recovers the clock and data from the SERDES, and parallelizes the data while synchronizing it with the receiver chip clock. This approach has the advantages of:

  1. Many fewer data errors due to data skewing.

  2. Higher data throughput.

  3. Lower hardware resources and hence lower costs.

  4. Lower power consumption in the hardware.

SERDES has been adopted in large scale internet switches and PCs. In fact, the PCI Express bus is a SERDES bus. For data centers with more than 10,000 microprocessors, SERDES offers much better potential for interconnect scaling, as a bus with 60 to 100 wires is replaced by ten two-wire ports.
This project is concerned with improving the data reliability of SERDES and building a complete built-in self-testing (BIST) system for SERDES. Ultimately, we want to make the hardware autonomically manage the data links to relieve the networking software of some of its burden. The clocking of the serial data in the SERDES system is of critical importance. The clocking out of the data is controlled by a phase-locked loop, and the clocking in of the data on the receive side is also controlled by a PLL in the clock and data recovery circuit. However, uncertainty, or jitter, in the exact time instant of the clock edge leads to erroneous data recovery, and that causes bit errors in the data. We have invented an analog jitter reduction circuit that uses the auto-correlation of the clock signal with itself in the immediately prior clock period to reshape the clock pulse to reduce the jitter. We have designed the circuit, created a chip layout for it, and analyzed its time-domain properties, poles and zeros, phase noise, and its susceptibility to process variations in making chips. On average, the transmit jitter was reduced by 62.24% and the receive jitter by 35.88%. The bit error rate (BER) was reduced from 10-12 to 6.44´10-20 for data being processed at 1 GHz.
We are now conducting more elaborate process variation studies for clock rates of 3 to 5 GHz, using supply voltage and temperature variations. Also, we are designing a BIST circuit for testing the device. The existing BER test method is to ship a huge number of bits over the SERDES, and calculate the fraction of erroneous bits received. This test is extraordinarily expensive, and we will eliminate it with the BIST hardware. A longer-term research project is to migrate some of the network management functions for these links into the SERDES hardware.
Interested Companies: Alcatel-Lucent, Xilinx, AMD, IBM, Broadcom, Qualcomm

  1. H. V. Venkatanarayanan and M. L. Bushnell, “A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits,” Proc. of the Int’l. Conf. on VLSI Design, 2008, pp 581-588, Invited Paper.

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