EFLAGS REGISTER
The EFLAGS register (Figure 3.9) indicates the condition of the processor and helps to control its operation. It includes the six condition codes (carry, parity, auxiliary, zero, sign, overflow, which report the results of an integer operation. In addition, there are bits in the register that maybe referred to as control bits Figure 3.9 PentiumII EFLAGS Register
• Trap flag (TF): When set, causes an interrupt after the execution of each instruction. This is used for debugging.
• Interrupt enable flag (IF When set, the processor will recognize external interrupts.
• Direction flag (DF): Determines whether string processing instructions increment or decrement the bit half-registers SI and DI (for bit operations) or the bit registers ESI and EDI (for bit operations.
• I/O privilege flag (IOPL): When set, causes the processor to generate an exception on all accesses to IO devices during protected-mode operation.
• Resume flag (RF Allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.
• Alignment check (AC Activates if a word or doubleword is addressed on a nonword or nondoubleword boundary.
• Identification flag (ID If this bit can beset and cleared, then this processor supports the processorID instruction. This instruction provides information about the vendor, family, and model.
• Nested Task (NT) flag indicates that the current task is nested within another task in protected- mode operation.
• Virtual Mode (VM) bit allows the programmer to enable or disable virtual 8086 mode, which determines whether the processor runs as an 8086 machine.
• Virtual Interrupt Flag (VIF) and Virtual Interrupt Pending (VIP) flag are used in a multitasking environment
Share with your friends: |
