A reference for Designing Servers and Peripherals for the Microsoft® Windows® 2000 Server Family of Operating Systems Intel Corporation and Microsoft Corporation Publication Date—June 30, 2000
IA-32 vs. IA-64 Miscellaneous Design Issues
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- Navigate this page:
- General Component Requirements
- System Microprocessor Requirements
- 2. Multiprocessor-capable system meets Windows requirements and minimum expansion requirements
- 2.3 IA-64 multiprocessor-capable system complies with ACPI 2.0
IA-32 vs. IA-64 Miscellaneous Design IssuesMemory. In this guide, IA-32 systems must support minimum memory capacity of 2 GB (for systems that provide support for fewer than 4 processors) or 8 GB (for systems with 4 or more processors). IA-64 systems must support a minimum RAM expansion capacity of 16 GB (for systems that provide support for fewer than 4 processors) or 32 GB (for systems with 4 or more processors). APIC support. In this guide, IA-32 systems must include Advanced Programmable Interrupt Controller (APIC) support that complies with ACPI 1.0b. IA-64 systems must include Streamlined APIC (SAPIC) support that complies with the 64-bit extensions defined in ACPI 2.0 Headless servers. In this design guide, Enterprise class IA-32 systems are required to support capabilities for “headless” server functionality; this is a recommendation for basic and SOHO class servers in this version of the design guide. Headless support is likely to become a requirement for all IA-32 systems in future versions of these guidelines. IA-64 systems are not required to support this capability. However, headless support is expected to become a requirement for IA-64 systems in future versions of these guidelines, when related support is provided in a future version of 64-bit Windows. Manageability. IA-32 systems must support manageability as defined in this document and in Windows Hardware Instrumentation Implementation Guide. In addition to this, IA-64 systems must implement hardware and firmware support for IA-64 Machine Check Architecture. Devices. IA-64 systems must not include legacy parallel ports and must provide a legacy serial port for use as a debug port. Chapter 2
This chapter presents requirements and recommendations that apply to the whole server system, including key components such as memory and power management. They apply to standard, high volume (or commodity) servers that run the Microsoft Windows 2000 Server operating system. Tips for selecting high-performance system components. For manufacturers who want to select high-performance components for server systems, the following are design features to look for when selecting components to improve memory performance:
Note: The system requirements defined in this publication provide guidelines for designing servers and peripherals that deliver an enhanced user experience when implemented with Windows 2000 Server. These requirements are not the basic system requirements for running any versions of the Windows 2000 Server operating system. General Component RequirementsThis section lists requirements and recommendations for system components such as memory and power management. 1. System and components properly support all datesRequired The firmware, real-time clock, system clocks, and the system as a whole must work correctly for all dates. System Microprocessor RequirementsThis section summarizes processor requirements for server systems. Note: It is recognized that OEMs supply systems with specific feature requirements to corporations, which can include providing servers that do not include any processors pre-installed before shipping. 2. Multiprocessor-capable system meets Windows requirements and minimum expansion requirementsRequired 2.1 Enterprise class server system supports expansion to at least four processors2.2 IA-32 multiprocessor-capable system supports ACPI 1.0bFor systems in which more than one processor can be installed, the system must employ those processors symmetrically; that is, all processors must be able to access all I/O buses and system memory, and cache coherency must be maintained. The system must also comply with the ACPI 1.0b specification. In addition, Advanced Programmable Interrupt Controller (APIC) support must comply with ACPI 1.0b by including the Multiple APIC Description Table defined in Section 5.2.8. Note that Windows 2000 and later versions of Windows use ACPI on all ACPI-based systems, and therefore compliance with MultiProcessor Specification, Version 1.4 (MPS 1.4) is no longer required. For information about the requirements for PCI IRQ routing on a multiprocessor ACPI system, see http://www.microsoft.com/hwdev/onnow/acpi-mp.htm. Note on Multiprocessor Wake-up: A problem has been uncovered with certain multiprocessor systems that will prevent them from properly waking up from a Sleep state under Windows 2000. This pertains to dual-processor or multi-processor systems that transition all processors from an active state to a STPCLK state, and more specifically to systems where all processors receive their STPCLK# request from one source. Prior to transitioning from a STPCLK state to a Sleep state or lower power state, all processors must generate a Stop Grant Bus cycle. It is essential that all processors have transitioned into the STPGNT state before it is safe to: 1) transition to a lower power state such as Sleep, or 2) externally shut off the processor clocks to allow for flushing buffers, cache maintenance, and other internal activities. For dual-processor and multiprocessor systems using a single STPCLK to all processors and a single SLP pin to all processors, the transition to the Sleep state should not be used. Behavior of the system during removal of the processor clock-such as transitions from STPCLK to Sleep state-cannot be guaranteed unless all STPGNT bus cycles are received. For example, Intel Xeon II Specification, “Section 4.2.5 Sleep State-State 5,” specifies that for a multiprocessor system, all processors are required to complete the Stop Grant bus cycle before the subsequent 100 BCLK waiting period and before the assertion of SLP# can occur. When multiple processors are serviced by a single STPCLK# request to all processors and a single SLP#, there is no provision to guarantee that all Stop Grant bus cycles are received before the assertion of SLP#. As another example, in 450NX-based platforms from Intel, the STPCLK# from PIIX4E is connected to all processors, and SLP# from PIIX4E is connected to all processors. The following sequence occurs: t0. Operating system writes PMCNTRL register. t1. PIIX4E asserts STPCLK#, then waits for Stop Grant acknowledgment. t3. The processor acknowledges with Stop Grant ACK cycle. t4. PIIX4E asserts SLP# after receiving this. This sequence works for uniprocessor systems (which is what the PIIX4E was originally designed for). However, in multiprocessor systems, SLP# might be asserted to a processor that is not in Processor Sleep State 3 (that is, not yet acknowledged). This premature SLP# assertion might result in a wake-up problem. Intel provides additional information about this issue through the Intel Technical Support Hotline at 1-800-628-8686 or 916-377-7000.
In addition, an IA-64 system must include a Multiple SAPIC Description Table that complies with ACPI 2.0. Note that MPS 1.4 support is not a requirement for systems with 64-bit processors and will not be used by any version of the 64-bit Windows operating system.
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