Chapter 1 Basic Principles of Digital Systems outlin e 1

Graphic Design File representation of a NAND Latch.

The documentation for MAX_PLUS II recommends that you do not create your

own latch circuits or similar cross-coupled structures. Rather, you should use primitives

such as LATCH, or components such as lpm_latch, which can be used in gdf

or vhd files.We will use the design in Figure 7.8 only to illustrate the function of a

NAND latch and to generate some timing data with the MAX_PLUS II simulator.

In order to make MAX_PLUS II synthesize this circuit as we have drawn it in Figure

7.8, we must select Global Project Logic Synthesis from the Assign Menu (Figure 7.9).

N O T E

In the resulting dialog box (Figure 7.10), we must choose the WYSIWYG (What You See

Is What You Get) synthesis style and check the box that says Multi-Level Synthesis for

MAX5000/7000 Devices.

FIGURE 7.9

Assign Menu

Choosing WYSIWYG Synthesis Style

When we compile the graphic file, MAX_PLUS II synthesizes the following equations,

which we can read in the project report file:

** EQUATIONS **

nR : INPUT;

nS : INPUT;

—— Node name is ‘nQ’ _ ‘:3’

—— Equation name is ‘nQ’, type is output

nQ _ LCELL( _EQ001 $ GND);

_EQ001 _ !nR

# !Q;

—— Equation name is ‘Q’, type is output

Q _ LCELL ( _EQ002 $ GND);

_EQ002 _ !nS

# !nQ;

We can rewrite the synthesized latch equations as:

nQ _ n_R_ _ Q_

➥ nd_latch.gdf

282 C H A P T E R 7 • Introduction to Sequential Logic

When we run the MAX_PLUS II Timing Analyzer, we get the delay matrix shown in

Figure 7.11. The delays are symmetrical for this circuit. The delay from nS to Q (7.5 ns) is

through one gate; from nS to nQ (12.5 ns) is through two gates. These values are the same

for the path from nR to nQ (7.5 ns; one gate) and from nR to Q (12.5 ns; two gates). We can

see these changes on simulation waveforms for the SET and RESET functions.

NAND Latch Delay Matrix (WYSIWYG Synthesis)

Figures 7.12 and 7.13 show the transition of a NAND latch from the RESET to the SET

condition. In Figure 7.12a, the latch is stable in the RESET condition (Q _ 0) at time t _ 0

(i.e., before a SET pulse is applied to the latch). At time t _ 0, the S_ input goes LOW (Figure

7.12b) and 7.5 ns later, the output Q goes HIGH (Figure 7.12c). This applies a HIGH

to the lower gate in the latch and at t _ 12.5 ns (Figure 7.12d), the Q_ output goes LOW,

closing the loop. The latch is now in a new stable configuration and the S_ input can go back

HIGH, as shown in Figure 7.12e.

Q _ 0

Q 1

_

0

Q _ 0

S _ 1

R _ 1

1

1

Q 0

_

1

Q _ 1 Q _ 0

S _ 0

R _ 1

Q _ 1

Q _ 1

RESET-to-SET transition

www.electronictech.com

7.2 • NAND/NOR Latches 283

The waveforms in Figure 7.13 also show this transition. The simulation window has a

2.5 ns grid, so three grid spaces are equivalent to 7.5 ns and five grid spaces to 12.5 ns. The

waveforms show Q going HIGH 7.5 ns after nS goes LOW, followed by nQ going LOW at

12.5 ns after nS.

Figures 7.14 and 7.15 show the same thing for the RESET function. The latch is in a

stable SET condition at time t _ 0 (Figure 7.14a). Input R_ goes LOW at t _ 0 (Figure

7.14b). At time t _ 7.5 ns, Q_ goes HIGH, which is transferred to the upper gate in the latch

circuit Figure 7.14c). Since both inputs of the upper gate are now HIGH, Q goes LOW at

time t _ 12.5 ns (Figure 7.14d). At this point the latch is stable in the RESET condition and

the input R_ can return to the HIGH (inactive) state, as shown in Figure 7.14e. Figure 7.15

shows the simulation waveforms for this transition.

NAND Latch SET function

simulation

S _ 1

0

_

R _ 0

S _ 1

0

_

R _ 1

S _ 1

1 1

_

0

0

R _ 1

S _ 1

R _ 0

Q _ 1

Q_1

SET-to-RESET Transition

NAND latch RESET function

simulation

284 C H A P T E R 7 • Introduction to Sequential Logic

Note that the latch is not stable in its new condition until the new logic levels have

propagated through both gates. Figure 7.16 shows the result of a RESET pulse that only

lasts for 7.5 ns. This pulse is too short to allow both gates to change states. The outputs

both oscillate, since the changing logic levels never “catch up” as they move around the

latch. This is due to the fact that both paths (nS-Q-nQ and nR-nQ-Q) are the same length.

If one path were slightly longer, the logic level controlled by the longer path would dominate

and the latch would stabilize in one state or the other.

NAND latch oscillation due to a

RESET pulse that is too short

Figure 7.17 shows a NAND latch with S_ _ R_ _ 0. This implies that both SET and

the output HIGH, both outputs respond by going HIGH. This condition is not unstable in

and of itself, but instability can result when the inputs change.

There are three possible results when the outputs go back to the HIGH state.

1. The SET input goes HIGH before the RESET input. In this case the latch resets, as

RESET is the last input active. This is shown in the simulation in Figure 7.18.

S _ 0

1

_

R _ 0

NAND Latch Forbidden State

SET goes HIGH before RESET

RESET goes HIGH before SET

2. The RESET input goes HIGH before SET. In this case, the latch sets, as shown in Figure

7.19.

3. The SET and RESET inputs go HIGH at the same time. This is an unstable case. Figure

7.20 shows how the latch will oscillate under this condition. When the inputs S_ and R_

are both LOW (Figure 7.20a), both latch outputs are HIGH. When S_ and R_ go HIGH

(Figure 7.20b), all gate inputs are HIGH. This makes both outputs LOW (Figure 7.20c).

The LOWs transfer across the latch to the opposite gates and, after a delay, make both

outputs HIGH (Figure 7.20d). At this point, oscillations will be sustained until the latch

is SET or RESET. The simulation waveforms in Figure 7.21 show the oscillatory condition

of the latch outputs.

Q _ 0

Q 1

_

1

Q _ 1

S _ 1

0

_

R _ 1

0

0

Q 1

_

1

1

R _ 0

S _ 1

R _ 1

Q _ 0

Q _ 0

NAND Latch Forbidden State Transition

In practice, the oscillatory condition of Figure 7.21 is unlikely to be sustained for very

long. One of the two gates is likely to be slightly faster than the other, which will allow one

state or the other to dominate.

FIGURE 7.21

SET and RESET go HIGH simultaneously

The operation of the NAND latch can be summarized in a function table, shown in

Table 7.2. The notation Qt_1 indicates that the column shows the value of Q after the specified

input is applied. Qt indicates the present state of the Q input.* Thus, the entry for the

no change state indicates that after the inputs S_ _ 0, R_ _ 0 are applied, the next state of the

output is the same as its present state.

*Many sources (such as data sheets) use the notation Q0 to refer to the previous state of Q. We will

use the notation indicated (Qt for present state and Qt_1 for next state) so as to be able to reserve Q0

for the least significant bit of a circuit requiring multiple Q outputs.

Table 7.3 shows the function table for the NOR latch.

The NAND latch shown previously (Figure 7.8) was synthesized in MAX_PLUS II, using

the WYSIWYG synthesis style. We did this so as to be able to use the MAX_PLUS II

simulation tool to get waveforms for a standard NAND latch. However, if we allow

MAX_PLUS II to synthesize the latch circuit in the Normal synthesis style, the software

will choose a more stable configuration, shown in Figure 7.22.

0 0 1 1 Forbidden

0 1 1 0 Set

1 0 0 1 Reset

1 1 Qt Q_t No Change

Table 7.3 NOR Latch Function Table

S R Qt_1 Q_t_1 Function

0 0 Qt Q_t No Change

0 1 0 1 Reset

1 0 1 0 Set

1 1 0 0 Forbidden

Vcc

nS

nR

NAND Latch as synthesized by

MAX_PLUS II (NORMAL

synthesis)

The equations for the circuit in Figure 7.22 from the MAX_PLUS II report file are

given as:

** EQUATIONS **

nR : INPUT;

nS : INPUT;

—— Node name is ‘nQ’

—— Equation name is ‘nQ’, location is LC117, type is output.

nQ _ LCELL( _EQ001 $ VCC);

_EQ001 _ nR & Q;

—— Node name is ´Q´ _ ´_2_1´

—— Equation name is ´Q´, location is LC115, type is output.

Q _ LCELL( _EQ002 $ !ns);

_EQ002 _ nR & nS & Q;

We can rewrite the above equations as:

Q _ (nR _ nS _ Q) _ n_S_

nQ _ (nR _ Q) _ 1 _ n_R_____Q_

Without going into a detailed analysis, we will just note that the latching occurs

through a combination of the XOR gate at Q and the feedback from the Q output to the 3-

input AND. The lower AND/XOR structure simply serves to invert the Q output to provide

a complementary value at nQ.

This configuration is more stable because both SET and RESET functions go through

the same path (the 3-input AND gate). Delay is the same from nS to Q and from nR to Q.

In the WYSIWYG version, the path is equal from nS to nQ and from nR to Q, but not from

nS to Q and nR to Q. The SET and RESET pulses thus go through different paths in the

WYSIWYG synthesis, resulting in unequal delays from the inputs to the Q output, which

can lead to instability.

Latch as a Switch Debouncer

Pushbutton or toggle switches are sometimes used to generate pulses for digital circuit inputs,

as illustrated in Figure 7.23. However, when a switch is operated and contact is made

on a new terminal, the contact, being mechanical, will bounce a few times before settling

into the new position. Figure 7.23d shows the effect of contact bounce on the waveform for

a pushbutton switch. The contact bounce is shown only on the terminal where contact is

being made, not broken.

Switches as Pulse Generators

Contact bounce can be a serious problem, particularly when a switch is used as an input

to a digital circuit that responds to individual pulses. If the circuit expects to receive

one pulse, but gets several from a bouncy switch, it will behave unpredictably.

A latch can be used as a switch debouncer, as shown in Figure 7.24a. When the pushbutton

is in the position shown, the latch is set, since S_ _ 0 and R_ _ 1. (Recall that the

NAND latch inputs are active LOW.) When the pushbutton is pressed, the R_ contact

NAND Latch as a Switch

Debouncer

288 C H A P T E R 7 • Introduction to Sequential Logic

bounces a few times, as shown in Figure 7.24b. However, on the first bounce, the latch is

reset. Any further bounces are ignored, since the resulting input state is either S_ _ R_ _ 1

(no change) or S_ _ 1, R_ _ 0 (reset).

Similarly, when the pushbutton is released, the S_ input bounces a few times, setting the

latch on the first bounce. The latch ignores any further bounces, since they either do not

change the latch output (S_ _ R_ _ 1) or set it again (S_ _ 0, R_ _ 1). The resulting waveforms

at Q and Q_ are free of contact bounce and can be used reliably as inputs to digital sequential

circuits.

❘❙❚ EXAMPLE 7.3 A NOR latch can be used as a switch debouncer, but not in the same way as a NAND latch.

Figure 7.25 shows two NOR latch circuits, only one of which works as a switch debouncer.

Draw a timing diagram for each circuit, showing R, S, Q, and Q_, to prove that the circuit in

Figure 7.25b eliminates switch contact bounce but the circuit in Figure 7.25a does not.

FIGURE 7.25

Example 7.3

NOR Latch Circuits

SOLUTION Figure 7.26 shows the timing diagrams of the two NOR latch circuits. In the

circuit in Figure 7.25a, contact bounce causes the latch to oscillate in and out of the forbidden

state of the latch (S _ R _ 1). This causes one of the two outputs to bounce for each

contact closure. (Use the function table of the NOR latch to examine each part of the timing

diagram to see that this is so.)

By making the resistors pull down rather than pull up, as in Figure 7.25b, the latch oscillates

in and out of the no change state (S _ R _ 0) as a result of contact bounce. The first

FIGURE 7.26

Example 7.3

NOR Latch Circuits

7.3 • Gated Latches 289

bounce on the SET terminal sets the latch, and other oscillations are disregarded. The first

bounce on the RESET input resets the latch, and further pulses on this input are ignored.

The principle illustrated here is that a closed switch must present the active input level

to the latch, since switch bounce is only a problem on contact closure. Thus, a closed

switch must make the input of a NOR latch HIGH or the input of a NAND latch LOW to

debounce the switch waveform.

The NOR latch is seldom used in practice as a switch debouncer. The pull-down resistors

need to be about 500 _ or less to guarantee a logic LOW at the input of a

TTL NOR gate. In such a case, a constant current of about 10 mA flows through the

resistor connected to the normally closed portion of the switch. This value is unacceptably

high in most circuits, as it draws too much idle current from the power

supply. For this reason, the NAND latch, which uses higher-value pull-up resistors

(about 1 k_ or larger) and therefore draws less idle current, is preferred for a

switch debouncer.

❘❙❚

7.2 Why is the input state S _ R _ 1 considered forbidden in the NOR latch? Why is the

same state in the NAND latch the no change condition?

7.3 Gated Latches

Gated SR latch An SR latch whose ability to change states is controlled by an

extra input called the ENABLE input.

steer a SET or RESET pulse to the correct input of an SR latch circuit.

when its ENABLE input is active.

Gated SR Latch

It is not always desirable to allow a latch to change states at random times. The circuit

shown in Figure 7.27, calleda gated SR latch, regulates the times when a latch is allowed

to change state.

The gated SR latch has two distinct subcircuits. One pair of gates is connected as an

SR latch. A second pair, called the steering gates, can be enabled or inhibited by a control

signal, called ENABLE, allowing one or the other of these gates to pass a SET or RESET

signal to the latch gates.

The ENABLE input can be used in two principal ways: (1) as an ON/OFF signal, and

(2) as a synchronizing signal.

Figure 7.27b shows the ENABLE input functioning as an ON/OFF signal. When ENABLE

_ 1, the circuit acts as an active-HIGH latch. The upper gate converts a HIGH at S

to a LOW at S_, setting the latch. The lower gate converts a HIGH at R to a LOW at R_, thus

resetting the latch.

When ENABLE _ 0, the steering gates are inhibited and do not allow SET or RESET

signals to reach the latch gate inputs. In this condition, the latch outputs cannot change.

K E Y T E R M S

N O T E

Figure 7.27c shows the ENABLE input as a synchronizing signal. A periodic pulse

waveform is present on the ENABLE line. The S and R inputs are free to change at random,

but the latch outputs will change only when the ENABLE input is active. Since the

fixed intervals. The outputs can change out of synchronization if S or R change when

short as possible.

Table 7.4 represents the function table for a gated SR latch.

FIGURE 7.27

Gated SR Latch

1 0 0 Qt Q_t No change

1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 0 0 Forbidden

0 X X Qt Q_t Inhibited

❘❙❚ EXAMPLE 7.4 Figure 7.28 shows two gated latches with the same S and R input waveforms but different

Draw the output waveforms, Q1 and Q2. Describe how the length of the ENABLE

pulse affects the output of each latch, assuming that the intent of each circuit is to synchronize

the output changes to the beginning of the ENABLE pulse.

Example 7.4

Effect of ENABLE Pulse Width

SOLUTION Figure 7.28b shows the completed timing diagram. The longer ENABLE

pulse at latch 1 allows the output to switch too soon during pulses 1 and 4. (“Too soon”

means before the beginning of the next ENABLE pulse.) In each of these cases, the S and R

inputs change while the ENABLE input is HIGH. This premature switching is eliminated in

latch 2 because the S and R inputs change after the shorter ENABLE pulse is finished. A

shorter pulse gives less chance for synchronization error, since the time for possible output

changes is minimized.

❘❙❚

Figure 7.29 shows the equivalent circuit of a gated D (“data”) latch, or transparent latch.

This circuit has two modes. When the ENABLE input is HIGH, the latch is transparent because

the output Q goes to the level of the data input, D. (We say, “Q follows D.”) When

the ENABLE input is LOW, the latch stores the data that was present at D when ENABLE

was last HIGH. In this way, the latch acts as a simple memory circuit.

The latch in Figure 7.29 is a modification of the gated SR latch, configured so that the

change) and S _ R _ 1 (forbidden) can never occur. However, the equivalent of the no

change state happens when the ENABLE input is LOW, when the latch steering gates are

inhibited.

Figure 7.30 shows the operation of the transparent latch in the inhibit (no change), set,

and reset states. When the latch is inhibited, the steering gates block any LOW pulses to the

latch gates; the latch does not change states, regardless of the logic level at D.

FIGURE 7.29

Transparent Latch

Operation of Transparent Latch

If EN _ 1, Q follows D. When D _ 1, the upper steering gate transmits a LOW to the

SET input of the latch and Q _ 1. When D _ 0, the lower steering gate transmits a LOW

to the RESET input of the output latch and Q _ 0.

Table 7.5 shows the function table for a transparent latch.