buffer, which represents a shared logic expander

about this type of buffer in Chapter 8, but for now, just be aware that this type of buffer supplies

inverted product terms for general use within the CPLD.

The Normal synthesis mode generates a sum-of-products equation that uses a number

of expanders, but only one logic cell (i.e., one SOP output), indicated as LC123. The

WYSIWYG synthesis uses an unnumbered output logic cell, which in turn uses two other

logic cell outputs (LC113 and LC114) as inputs. Thus, in the Normal synthesis mode, the

input signals propagate through one logic cell, and in the WYSIWYG mode, the input

signals go through two layers of logic cells, increasing the path length, and thus the delay.

What can we conclude? If MAX_PLUS II is allowed to synthesize a design for a full

adder in the defined Normal style, it will optimize the design equations to produce as flat a

network as possible. Thus we do not need to explicitly design an adder circuit to have a fast

carry function.

Summary 267

S U M M A R Y

1. Addition combines an addend (x) and an augend (y) to get a

sum (z _ x _ y).

2. Binary addition is based on four sums:

0 _ 0 _ 0

0 _ 1 _ 1

1 _ 1 _ 10

1 _ 1 _ 1 _ 11

3. A sum of two bits generates a sum bit and a carry bit. (For the

first two sums above, the carry bit is 0; the last two sums

have a carry of 1. The last sum includes a carry from a lowerorder

bit.)

get a difference (z _ x _ y).

5. Binary subtraction is based on the following four differences:

0 _ 0 _ 0

1 _ 0 _ 1

1 _ 1 _ 0

10 _ 1 _ 1

6. If the subtrahend bit is larger than the minuend bit, as in the

fourth difference above, a 1 must be borrowed from the next

higher-order bit.

7. Binary addition or subtraction can be unsigned, where the

magnitudes of the operands and result are presumed to be

positive, or signed, where the operands and result can be positive

or negative. The sign is indicated by a sign bit.

8. The sign bit (usually MSB) of a binary number indicates that

the number is positive if it is 0 and negative if it is 1.

9. Signed binary numbers can be written in true-magnitude, 1’s

complement, or 2’s complement form. True magnitude has

the same binary value for positive and negative numbers,

with only the sign bit changed. A 1’s complement negative

number is generated by inverting all bits of the positive number

of the same magnitude. A 2’s complement negative number

is generated by adding 1 to the equivalent 1’s complement

number. Positive numbers are the same in all three

forms.

10. 1’s complement or 2’s complement binary numbers are used

by adding a negative number in complement form to another

number in complement form (i.e., x _ y _ x _ (_y)). This

technique does not work for true-magnitude form.

11. A negative sum or difference in 2’s complement subtraction

must be converted to a positive form to read its magnitude

(i.e., _(_x) __x).

12. A signed binary number, x, with n bits has a valid range of

_2n _ x _ _( 2n _1).

13. A negative number with a power-of-2 magnitude (i.e.,

_2n) is written in 2’s complement form as n 0s preceded

by all 1s to fill the defined size of the number (e.g., in 8-

bit 2’s complement form, _128 _ 10000000 (1 followed

by seven 0s; 128 _ 27); in 8-bit 2’s complement form, _8 _

11111000 (all 1s, followed by three 0s; 8 _ 23).

14. If a sum or difference falls outside the permissible range of

magnitudes for a 2’s complement number, it generates an

overflow into the sign bit of the number. The result is that

the sum of two positive numbers appears to be negative

(e.g., 01111111 _ 00000010 _ 10000001; 127 _ 2 _

129) or the sum of two negative numbers appears to be

positive (e.g., 11111111 _ 10000000 _ 01111111, where

the carry beyond the 8th place is discarded: _1 _ (_128) _

_129).

than 15 (F) can be converted to a hexadecimal value by subtracting

16 and carrying a 1 to the next digit position.

16. Hexadecimal numbers can be subtracted conventionally or

by a complement method. To get the 16’s complement of a

number, obtain the 15’s complement by subtracting the number

from all Fs and adding 1 to the result.

17. Binary numbers can be used in nonpositional codes to represent

numbers or alphanumeric characters.

18. Binary coded decimal (BCD) codes represent decimal numbers

as a series of 4-bit groups of numbers. Natural BCD or

8421 code does this as a positionally weighted code for each

digit (e.g., 158 _ 0001 0101 1000 (NBCD)). Other codes,

such as Excess-3, are not positionally weighted.

19. Gray code is a binary code that has a difference of one bit

between adjacent codes. It can be generated by a set of

XOR functions or by recognizing the symmetry inherent in

the code. In any Gray code sequence, the MSB is 0 for the

first half of the sequence and 1 for the second half. The remaining

bits are symmetrical about the halfway point of the

sequence.

20. ASCII code represents alphanumeric characters and computer

control codes as a 7-bit group of binary numbers. Alpha

characters are listed in uppercase in columns 4 and 5 of

the ASCII table. Lowercase alpha characters are in columns

6 and 7. Numeric characters are in column 3.

21. A half adder combines two bits to generate a sum and a carry.

It can be represented by the following truth table:

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

A B COUT _

0 0 0 0

1 0 0 1

22. From the half adder truth table, we can derive two equations:

_ _ A _ B

23. Afull adder can accept an input carry from a lower-order adder

and combine the input carry with two operands to generate

a sum and output carry. Its operation can be summarized in

the following truth table:

31. The port map of a component maps the port names defined in

a component to the port, signal, or variable names defined in

the design entity that uses the component.

32. If all ports of a component are to be used in the same order as

in the component definition in the original component design

entity, the port map can simply contain the user names in the

same order. For example:

adder1: full_add PORT MAP (a(1), b(1),

c0, c(1), sum(1));

33. If only a portion of the component ports are to be used or

they are not used in the same sequence as they are declared,

the port map must be more explicit. For example:

adder1: full_add

PORT MAP ( b __ b(1),

a __ a(1),

c_in __ c0,

sum __ sum(1)),

c_out __ c(1);

34. A GENERATE statement can be used to instantiate multiple

instances of a component. The GENERATE statement has

the form:

label:

FOR index IN range GENERATE

END GENERATE;

35. MAX_PLUS II will synthesize an adder to minimize carry

delays without much intervention.

36. A parallel binary adder can be made into a 2’s complement

subtractor by inverting one set of inputs and tying the input

carry to a logic HIGH.

37. A parallel binary adder can be made into a 2’s complement

adder/subtractor by using a set of XOR gates as programmable

inverters and connecting the XOR control line to the

carry input of the adder.

38. One method of detecting a sign bit overflow in a 2’s complement

adder/subtractor is to compare the sign bits of the

operands to the sign bit of the result. If the sign bits of

the operands are the same as each other, but different

from the sign bit of the result, there has been an overflow.

The Boolean equation for this detector is given by V _ S__ _

SA _ SB _ S_ _ S_A _ S_B.

39. Another method of overflow detection compares the carry

out of the MSB of the adder/subtractor to the carry into

the MSB. An overflow occurs if there is a carry out of or

into the MSB, but not both. The Boolean equation for this

detector is given by V _ Cn _ Cn_1, for an n-bit

adder/subtractor.

40. A BCD adder adds two binary coded decimal (BCD) digits

and generates a BCD digit and a carry bit.

41. Since BCD is a 4-bit code, BCD addition can be done with a

4-bit binary adder and a code converter. The code converter

can be synthesized from another 4-bit binary adder and a circuit

to generate a carry.

A B CIN COUT _

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

24. The following Boolean equations for a full adder can be derived

from the truth table and Boolean algebra:

COUT _ (A _ B) CIN _ AB

_ _ (A _ B) _ CIN

25. Two half adders can be combined to make a full adder.

Operands A and B go to the first half adder. The sum output

of the first half adder and the carry input go to the inputs of

the second half adder. The carry outputs of both half adders

are combined in an OR gate.

26. Multiple full adders can be cascaded to make a parallel binary

adder. Operands A1 and B1 are applied to the first full

adder. Carry bit C0 is grounded. A2 and B2 go to the second

adder stage, and so on. The carry output of one stage is cascaded

to the carry input of the following stage. This connection

is called ripple carry.

27. Ripple carry has the disadvantage of increasing the time required

to generate an output result as more stages are

added. Fast carry, or look-ahead carry, examines all adder

inputs simultaneously and generates each internal and output

carry with a separate circuit. This makes the carry circuit

wider, but flatter, thus reducing the delay time of the

circuit.

design entity for a full adder, then using multiple instances of

the full adder as components in the parallel adder.

29. To use a component in a VHDL design hierarchy, we require

a design entity that defines the component, a component declaration

in the design entity that uses the component, and a

component instantiation statement for every instance of the

component in the higher-level design entity.

30. The general form of a design entity using components is:

ENTITY entity_name IS

PORT ( input and output definitions);

END entity_name;

ARCHITECTURE arch_name OF entity_name IS

component declaration (s);

signal declaration(s);

BEGIN

Other statements;

END arch_name;

Glossary 269

G L O S S A R Y

1’s complement A form of signed binary notation in which

negative numbers are created by complementing all bits of a

number, including the sign bit.

10’s complement A way of writing decimal numbers where a

negative number is generated by adding 1 to its 9’s complement.

negative numbers are created by adding 1 to the 1’s complement

form of the number.

8421 Code (or NBCD; natural binary coded decimal) A

BCD code that represents each digit of a decimal number by its

4-bit true binary value.

9’s complement A way of writing decimal numbers where a

number is made negative by subtracting each of its digits from 9

(e.g., _726 _ 999 _ 726 _ 273 in 9’s complement).

Addend The number in an addition operation that is added to

another.

and numerical characters.

A 7-bit code for representing alphanumeric and control

characters.

Augend The number in an addition operation to which another

number is added.

of a decimal number by a 4-bit binary value.

bits, each group representing a BCD digit.

when the subtrahend digit is larger than the minuend digit.

position when the sum of two single digits is too large to be

expressed as a single digit.

Carry bit A bit that holds the value of a carry (0 or 1) resulting

from the sum of two binary numbers.

often for the purpose of expanding the number of bits

available for a particular function.

Case shift Changing letters from capitals (UPPERCASE) to

small letters (lowercase) or vice versa.

as a part of a higher-level file in a hierarchical design.

the input and output port names of a component used in a VHDL

design entity.

Component instantiation statement A statement that maps

port names of a VHDL component to the port names, internal

signals, or variables of a higher-level VHDL design entity.

Difference The result of a subtraction operation.

End-around carry An operation in 1’s complement subtraction

where the carry bit resulting from a sum of two 1’s complement

numbers is added to that sum.

Excess-3 code A BCD code that represents each digit of a decimal

number by a binary number derived by adding 3 to its 4-bit

true binary value. Excess-3 code has the advantage of being

“self-complementing.”

inverted product term for general use within a CPLD.

a carry bit directly from all incoming operand bits, independent

of the operation of each full adder stage.

Full adder A circuit that will add a carry bit from another full

or half adder and two operand bits to produce a sum bit and a

carry bit.

GENERATE statement A VHDL construct that is used to

create repetitive portions of hardware.

bit changes between two successive codes.

bit and a carry bit.

levels or layers in which complete designs form portions of another,

more general design entity. The more general design is

considered to be the higher level of the hierarchy.

how large the number is (i.e., its magnitude).

another number is subtracted.

(e.g., in the expression x _ y _ z, x and y are the operands).

number which results from a sum larger than can be represented

by the number of magnitude bits.

Parallel binary adder A circuit, consisting of n full adders,

which will add two n-bit binary numbers. The output consists of

a parallel adder to the next by connecting COUT of one full adder

to CIN of the following stage.

Self-complementing A code that automatically generates a

negative-equivalent (e.g., 9’s complement for a decimal code)

when all its bits are inverted.

Sign bit A bit, usually the MSB, that indicates whether a

signed binary number is positive or negative.

using signed binary numbers.

whose sign is represented by one bit, usually the most significant

bit, and whose magnitude is represented by the remaining

bits.

time that can be expected of a CPLD.

from another number.

sum of two 1-bit binary numbers.

whose magnitude is represented in true binary.

using unsigned binary numbers.

indicated by a sign bit. A positive sign is assumed unless explicitly

stated otherwise.

P R O B L E M S

1’s complement, and 2’s complement forms.

(addition only), 1’s complement, and 2’s complement

systems. Use 8-bit numbers consisting of a sign

bit and 7 magnitude bits. (The numbers shown are in the

decimal system.)

Convert the results back to decimal to prove the correctness

of each operation. Also demonstrate that the idea

of adding a negative number to perform subtraction is not

valid for the true-magnitude form.

a. 37 _ 25

b. 85 _ 40

c. 95 _ 63

d. 63 _ 95

e. _23 _ 50

f. 120 _ 73

g. 73 _ 120

6.5 What are the largest positive and negative numbers, expressed

in 2’s complement notation, that can be represented

by an 8-bit signed binary number?

6.6 Perform the following signed binary operations, using 2’s

complement notation where required. State whether or

not sign bit overflow occurs. Give the signed decimal

equivalent values of the sums in which overflow does not

occur.

a. 01101 _ 00110

b. 01101 _ 10110

c. 01110 _ 01001

d. 11110 _ 00010

e. 11110 _ 00010

6.7 Without doing any binary complement arithmetic, indicate

which of the following operations will result in 2’s

complement overflow. (Assume 8-bit representation consisting

of a sign bit and 7 magnitude bits.) Explain the

reasons for each choice.

a. _109 _ 36

b. 109 _ 36

c. 65 _ 72

d. _110 _ 29

e. 117 _ 11

f. 117 _ 11

6.8 Explain how you can know, by examining sign or

magnitude bits of the numbers involved, when overflow

has occurred in 2’s complement addition or subtraction.

Section 6.4 Hexadecimal Arithmetic

6.9 Add the following hexadecimal numbers.

a. 27H _ 16H

b. 87H _ 99H

c. A55H _ C5H

d. C7FH _ 380H

e. 1FFFH _A80H

Problems 271

8421 BCD code, and Excess-3 code.

to the range from 010 to 3110.

over $50. (Monday only)”