• Universal PAL and Generic Array Logic (GAL) 347

Pin 11 provides an active-LOW Output Enable function. This is selected by local

architecture cells to provide control of the output tristate buffer, either from theO__Epin or from

a product term in theANDmatrix. If theO__Efunction is unused, the pin can be used as an input.

GAL22V10

Figure 8.18 shows the logic diagram of a GAL22V10 generic array logic device.

This industry-standard device has a number of features that make it superior to the

PALCE16V8.

Macrocell Configurations for a PALCE16V8 PLD (Courtesy of Lattice Semiconductor Corporation)

D Q D Q

OE OE

CLK CLK

Note 1 Note 1

Note 2

Notes: Adjacent I/O pin

the combinatorial output mode.

2. This configuration is not available on pins 15 and 16.

Q Q

1 1

1 0

SL04

D Q

0 X

1 0

0 1

1 1

SG1 SL04

I/O5 17

I/O7 19

0 3 2324

31

16

8

15

7

4 7 8 1112 15 16 19 20 27 28 31

1 1

1 0

SL06

D Q

0 X

1 1

0 0

1 0

0 X

VCC

0 X

SL17

SG1

1 0

1 0

1 0

0 1

1 1

SG0 SL07

VCC

1 1

1 0

SL05

D Q

0 X

1 1

0 0

1 0

0 X

VCC

CLK/I0 1

I2 3

I4 5

Q

Q

Q

FIGURE 8.17 (a)

PALCE16V8 Logic Diagram (Courtesy of Lattice Semiconductor Corporation)

8.5 • Universal PAL and Generic Array Logic (GAL) 349

1 1

1 0

SL00

D Q

0 X

1 1

0 0

1 0

0 X

56

63

55

40

32

39

VCC

0 X

SL12

SG1

1 0

1 0

1 0

0 1

1 1

SG1 SL02

1 1

1 0

SL03

D Q

0 X

1 1

0 0

1 0

0 X

I/O3 15

I/O1 13

VCC

1 1

1 0

SL01

D Q

0 X

1 1

0 0

1 0

0 X

VCC

0 34 7 8 1112 15 16 19 20 2324 27 28 31

I8

I/O0 12

10

9

I6 7

Q

Q

Q

FIGURE 8.17 (b)

(PALCE16V8 Logic Diagram

350 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.18

GAL22V10 Logic Diagram

1. There are more outputs (10 as opposed to 8 for the 16V8).

2. There are more inputs (11 dedicated inputs, plus any I/O lines used as inputs).

3. The output logic macrocells are of different sizes, allowing expressions with larger

numbers of product terms in some OLMCs than others. There are two OLMCs with

each of the following numbers of product lines: 8, 10, 12, 14, and 16. This allows more

flexibility in design, while minimizing the number of product lines.

GAL22V10 OLMC Configurations

4. OLMC configuration is much simpler than that of a PALCE16V8. Two architecture

cells per macrocell, S0 and S1, select the output type, as shown in Figure 8.19.

5. There are product lines for Synchronous Preset (SP) and Asynchronous Reset (AR). The

SP line sets all flip-flops HIGH on the first clock pulse after it becomes active. The AR

line sets all flip-flops LOW as soon as it activates, without waiting for the clock pulse.

(Note that these lines set or reset the Q output of each flip-flop. An active-LOW registered

output inverts this state at the output pin.)

of several interconnected programmable blocks.

in a CPLD.

connections that link together the Logic Array Blocks of a CPLD.

K E Y T E R M S

Buried logic Logic circuitry in a PLD that has no connection to the input or output

pins of the PLD, but is used solely as internal logic.

switching used in a macrocell output.

macrocells in the same LAB.

programmable AND matrix of an LAB for use by any other macrocell in the LAB.

Figure 8.20 shows the block diagram of an Altera MAX7000S Complex PLD (CPLD).

A device of this type—the EPM7128SLC84—is one of the two devices installed on the

Altera UP-1 University Program board, so we will use it as a specific example of the

MAX7000S family of devices.

INPUT/GCLK1

INPUT/GCLRn

INPUT/OE2/GCLK2

INPUT

Macrocells

PIA

17 to 32

33 to 48

49 to 64

Control

I/O

Block

Control

I/O

Block

6 to 16 16

36

6 to 16

6 to 16 I/O Pins

6 to 16 6 to 16

6 to 16 16 16

36 36

6 6

6 to 16

6 Output Enables

LAB A

LAB C

LAB D

6 to 16

16

36

6 to 16

6 to 16 I/O Pins

6 to 16 I/O Pins

FIGURE 8.20

MAX 7000E and MAX 7000S Device Block Diagram (Courtesy of Altera)

The part number breaks up as follows:

EPM7 MAX7000 family

128 number of macrocells

S in-system programmable

LC84 84-pin PLCC package

8.6 • MAX7000S CPLD 353

The main structure of the MAX7000S is a series of Logic Array Blocks (LABs),

linked by a Programmable Interconnect Array (PIA). Each LAB is a group of

16 macrocells that can share common product terms and lend or borrow unused product

terms among each other. A single LAB has similar I/O and programming capability to a

low-density PLD, so a CPLD like the MAX7000S can be thought of as an array of interconnected

PALs or GALs on a single chip.

An EPM7128S has 8 LABs, for a total of 8 _ 16 _ 128 macrocells. However, these

are not all available to the user as I/Os; the number of available I/O pins depends on the device

package. Figure 8.20 indicates that each LAB in a MAX7000S device has from 6 to

16 I/O pins. For an EPM7128S in a 160-pin PQFP package, there are 12 I/Os per LAB, for

a total of 96 available pins. For the same device in an 84-pin PLCC package, there are only

8 I/Os per LAB, for a total of 64 pins.

In practice, if an EPM7128SLC84 is to be programmed in-circuit (i.e., while installed

on a circuit board), there are only 60 I/Os available, as four pins are required for the programming

interface. The macrocells that are not connected to user I/O pins can only be

used for buried logic, or logic that is internal to the chip only.

As implied in Figure 8.20, all I/O pins connect to and from their associated LAB via

an I/O Control Block (a circuit that controls the tristate switching of signals at an I/O pin).

The I/O pin signals also connect directly to the PIA, where they are available for use in

other LABs. Sixteen lines connect the macrocell outputs of each LAB to the PIA, again for

use throughout the device. The PIA communicates to each LAB via 36 product lines to

provide connections from other LABs.

The MAX7000S family has four pins that can be configured as control signals or

inputs. GCLK1 is a global clock that is common to all macrocells in the device and can

be used to synchronously clock all registers. OE1 is an output enable that can globally

activate or disable the tristate outputs of the device macrocells. GCLRn is an active-

LOW global clear function. The fourth control pin can be configured as an input, as can

the other three pins, or as a second global clock (GCLK2) or output enable (OE2). If

the control functions are not used, these pins add four inputs to the available total.

These assignments can be made by the MAX_PLUS II software during the design

process.

that of a GAL or Universal PAL in that it provides a sum-of-products function with active-

HIGH or -LOW options and the choice of registered or combinational output. Registered outputs

can be clocked with one of two global clocks or by a product term from the AND matrix.

The register can be cleared globally or by a product term and preset with a product term.

The macrocell has five dedicated product terms, which is fewer than found in the PAL

and GAL matrices we examined earlier. This is generally sufficient to implement most

logic functions. If more terms are required, they can be supplied by a set of shared logic

Shared logic expanders do not add more product terms to a given macrocell. They

do make the programming of the entire LAB more efficient by allowing a product term

to be programmed once and used in several macrocells of the same LAB. One product

term per macrocell is inverted and fed back into the shared expander pool of product

terms. Since there are 16 macrocells per LAB, the shared logic expander pool has up to

16 product terms.

Parallel logic expanders allow a macrocell to borrow up to 15 product terms from its

three lower-numbered neighbors (5 product terms per neighboring macrocell). For example,

macrocell 4 can borrow up to 5 terms each from macrocells 3, 2, and 1. By using its 5

dedicated product terms and the maximum number of parallel expanders, a macrocell can

have up to 20 product terms at its disposal. These borrowed terms are not usable by the

macrocell from which they were borrowed. The parallel expanders are set up so that a

lower-number cell lends product terms to a higher-number cell, so the number of available

terms depends on how close to the end of a chain a macrocell is. Expander assignments are

done automatically by MAX_PLUS II at compile time.

by storing a list of output values that correspond to all possible input combinations.

as a look-up table.

function to expand beyond the width of one logic element.

functions between logic elements.

CPLD (2048 bits in a FLEX10K device), used for implementing complex logic

functions in look-up table format.

All programmable logic devices we have seen until now have been based on sum-ofproducts

arrays. Another major type of PLD is based on look-up table (LUT) architecture.

In this architecture, a number of storage elements are used to synthesize logic functions by

storing each function as a truth table. To illustrate the look-up table concept, let us use the

truth table of a 2-bit equality comparator, shown in Table 8.2.

The comparator examines inputs A1A0 and B1B0 and makes output AEQB equal to

logic 1 if A1A0 _ B1B0. If we were to implement the circuit as an SOP array, we would first

find the Boolean expression by combining the four product terms from the truth table and

then program the appropriate cells in a CPLD AND matrix. The look-up table implementation

of this function is based on a totally different concept.

K E Y T E R M S

Product-

Term

Matrix

Product Terms

36 Signals

from PIA

Select

Enable

Register

to I/O

Block

from

Global

Global

Parrellel Logic

Expanders

(from other

macrocells)

Shared Logic

Expanders

Programmable

Register

Fast Input

Select

VCC

CLRN

ENA

MAX 7000E and MAX 7000S Device Macrocell (Courtesy of Altera)

A1

A0

B0

AEQB

LUT

Storage

D Q

D Q

D Q

ADDR0

ADDR15

ADDR1

Address decoder

A1

A0

B1

Look-up Table

Figure 8.22 shows the structural concept of a 4-bit look-up table circuit. An array of 16

flip-flops (Q0 through Q15) contain data for all possible combinations of A1A0B1B0, one

flip-flop per combination. The LUT inputs A1A0B1B0 are decoded by an internal address

decoder. Each decoder output activates a tristate buffer that passes or blocks the output of

one flip-flop. The active buffer passes the contents of the flip-flop to AEQB; all other

buffers are in the high-impedance state, blocking the data from the other flip-flops.

The contents of the flip-flops are loaded when the look-up table is configured (programmed)

with the required function. After that the flip-flops retain their information until

they are reconfigured. For our comparator example, flip-flops 0, 5, 10, and 15 are all set

(Q_1).All other flip-flops are reset (Q_0). Examine Table 8.2 to confirm that this is true.

The 16-bit storage element in Figure 8.22, combined with switching to choose a combinational

or registered output and to interconnect with other parts of the chip, is called a

logic element (LE). A logic element performs a function similar to that of a macrocell in

SOP-type PLDs.

Figure 8.23 shows the structure of a logic element in an Altera FLEX10K CPLD. In

addition to the LUT, the LE has circuitry to select various control functions, such as clock

and reset, a flip-flop for registered output, some expansion circuitry (cascade and carry),

and interconnections to local and global busses.

The cascade chain circuit, shown in Figure 8.24 allows the user to program

Boolean functions with more than four inputs, thus requiring more than one LUT. The

Comparator

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 0

0 0 1 1 3 0

0 1 0 0 4 0

0 1 0 1 5 1

0 1 1 0 6 0

0 1 1 1 7 0

1 0 0 0 8 0

1 0 0 1 9 0

1 0 1 0 10 1

1 0 1 1 11 0

1 1 0 0 12 0

1 1 0 1 13 0

1 1 1 0 14 0

1 1 1 1 15 1

356 C H A P T E R 8 • Introduction to Programmable Logic Architectures

d[3..0] LUT

LE1

LE2

LEn

LE1

LE2

LEn

Cascade Chain Operation (Courtesy of Altera)

FLEX10K Logic Element (Courtesy of Altera)

DATA3

DATA2

DATA4

LABCTRL2

Reset

LABCTRL4

Clock

Cascade-Out

Clear/

Preset

to FastTrack

Interconnect

to LAB local

Interconnect

Look-Up

(LUT)

Chain

Chain

ENA

D Q

Register Bypass Programmable

Register

8.7 • FLEX10K CPLD 357

a1 s1

LUT

Chain

Carry-In

b2

LUT

Chain

LE1

an sn

LUT

Chain

LUT Carry-Out

Carry

Chain

LEn

Carry Chain Operation

(n-bit Full Adder)

(Courtesy of Altera)

cascade chain can be AND- or OR-type, depending on what DeMorgan equivalent form is

most appropriate.

The carry chain, shown in Figure 8.25 allows for efficient fast-carry implementation

of adders, comparators, and other circuits that depend on the combination of low-order

bits to define high-order functions (i.e., circuits whose inputs become wider with higherorder

bits). Figure 8.25 shows the carry chain as implemented by an n-bit adder.

A Logic Array Block (LAB), shown in Figure 8.26, consists of eight logic elements

and a local interconnect. The LAB is connected to the rest of the device by a series of row

and column interconnects, which Altera calls a FastTrack Interconnect. Figure 8.27 shows

the overall structure of a FLEX10K device, with several LABs and a number of

Carry-In and

Cascade-In

Carry-Out and

Cascade-Out

LE1

LE3

LE5

LE7

Dedicated Inputs and

Global Signals

2 8 24

LAB Local

Interconnect

LAB Control

Signals

Column-to-Row

Column

Row Interconnect

4

4

4

4

4

4

4

8 2

16

8

FIGURE 8.26

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