Note 2: All voltages are measured with respect to GND, unless othewise specified. Note 3

than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more

than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900 VDC

over temperature variations, initial tolerance and loading.

if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages

can be adjusted to achieve this. See Figure 13.

Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little

temperature dependence (Figure 6). See paragraph 4.0.

www.national.com 4

Extract from ADC0808 Datasheet (Reprinted with permission of National Semiconductor)

UP-1 board, we must also include a clock divider circuit. The Altera UP-1 board has an onboard

oscillator that runs at 25.175 MHz. The clock rate, as defined by the ADC0808 data

sheet, must be in the range 10kHz _ fc _ 1280 kHz.

A 5-bit counter can serve as a divide-by-32 circuit (25 _ 32), as shown in Figure

12.41. If the UP-1 oscillator is applied to the counter clock, the Q4 output frequency is

given by 25.175 MHz/32 _ 786.7 kHz, which is within the required range for the ADC

clock. Q4 should then be used to clock the state machine, as well as any other synchronous

circuitry used in conjunction with the ADC0808.

We can make a few minor changes to the ADC interface in Figure 12.38 to make it run

as a continuous-conversion circuit. First, we eliminate the go input and associated pushbutton.

Second, we change the state diagram to eliminate the idle state, as shown in Figure

12.42. With no pushbutton to press and then release, we eliminate two wait transitions

(previously associated with the idle and start states) from the state diagram. Otherwise,

the circuit and controller remain the same. A simulation of the modified controller is shown

in Figure 12.43.

Analog sources ADC0808

Channel

LATCH

D6

D7

D4

D2

D0

D3

D7

D5

SC

OE

GO

CLOCK

D2

D1

VCC

START

ALE

CONTROLLER

ADD A

IN 1

IN 7

ADD C

Q3

Q6

Q5

Q4

Q1

Q0

Q6

Q7

Q4

EN

Q2

Q1

RESET

RESET

VCC

ADC Interface with One Output Channel and Manual Input Channel Selection

go,eoc/sc,oe,en

X X /000

X X /010

X0/000

0X/000

0X/000

store start

wait 1

read

wait 2

State Diagram for an ADC

Controller

FIGURE 12.40

Simulation of State Machine

ADC Controller

CTR DIV 32

25.175 MHZ

786.7 KHZ

Q0

Q3

Q4

Q2

Q1

5-Bit Counter as Divide-by-32 Clock Divider

❘❙❚ EXAMPLE 12.13 From the ADC0808 data sheet extract in Figure 12.37, determine the number of clock cycles

required for the conversion of an analog signal.

Solution For a clock frequency of 640 kHz, typical conversion time is given as 100 _s.

640 _ 103 clock cycles

_ (100 _ 10_6 seconds) _ 64 clock cycles

second

ADC0808 controlled by a state machine represented by the state diagram of Figure 12.42

if the system clock frequency is 787 kHz.

Solution One conversion cycle, Ts, requires 64 clock cycles for the ADC and an

overhead of 13 clocks _2 _s for the state machine for a total of 77 clock cycles _2

_s. (Start to wait1 requires one clock cycle. An additional 8 cycles _2 _s are needed

before eoc goes LOW. According to Note 7 in Figure 12.37, the ADC conversion is

complete one clock cycle before EOC goes HIGH. From this point back to start is 4

clocks.)

X /000

1/011

X/100

0/000

read wait 2

start

FIGURE 12.42

State Diagram for Continuous-

Convert ADC Controller

FIGURE 12.43

Simulation of Continuous-

Conversion ADC Controller

12.4 • Data Acquisition 611

According to the Nyquist sampling theorem, the maximum-frequency component of

the sampled analog signal is fmax _ fs/2 _ 10.02 kHz/2 _ 5.01 kHz. This is of the same order

of magnitude as a telephone-quality audio signal.

❘❙❚

CPLD-Based Data Acquisition Network

from four analog channels. All the circuitry within the broken line is contained within a

single CPLD, such as the Altera EPM7128SLC84. The operation is similar to the system in

T

f

T

s

s

s









−

1

787 10

1 1

10 02

6

6

clock cycles + 2 s = 99.8 10 seconds

s

kHz

.

.

Analog sources ADC0808

D[7..0]

SC

OE

CLK

CLK

CONTROLLER

ADD A

IN1

IN2

IN4

IN6

OE

ADD B

EOC

CNT_EN

CNT_EN

CLK

Q0

Q1 CPLD

DECODER

D[7..0]

Q[7..0] Q0[7..0]

Q1[7..0]

Q2[7..0]

Octal latch

EN

D[7..0]

Q[7..0]

EN

D[7..0]

Q[7..0]

EN

D[7..0]

Q[7..0]

D1

D0

Y0

Y2

4-Channel Data Acquisition System

Figure 12.38, except that with multiple latches in the circuit, a counter and decoder are required

to keep track of the selected channel.

The controller, whose state diagram is shown in Figure 12.45, generates the same control

signals for the ADC as the system in Figure 12.38. When the conversion is complete

and the controller detects a LOW on its eoc input, it reads the ADC output and transfers the

contents to the selected 8-bit latch. The latch is selected, via the decoder, by the value of

the counter (e.g., Q1Q0 _ 11 selects analog input channel 3, decoder output Y3, and latch

3). The selected latch input is enabled (i.e., made transparent) by the controller during the

transition from wait2 to read. At all other times all decoder outputs are LOW, disabling all

latches, thus placing them in store mode. After the ADC data have been stored, the controller

sets cnt_en HIGH, which allows the counter to be incremented on the next clock

pulse. The next channel is now ready for a convert-and-store cycle. After all channels have

been sampled, converted, and stored, the cycle begins again at channel 0 and continues indefinitely.

eoc/sc,oe,cnt_en, latch_en

X /0000

X /0100 1/0101

0/0000

X/1000

0/0000

wait 2

start

State Diagram for 4-channel Data Acquistion System

Figure 12.46 shows a simulation of the controller, counter, and decoder for the data

acquisition system of Figure 12.44. During the read-and-store part of the cycle, only

one of the latch enables, y0 to y3, is active when oe is active. The number of the active

latch enable is the same as the counter value on the second last waveform. The last line

in the simulation (controlleroutputs3.Q) is the cnt_en line from the controller to the

counter. The counter is incremented on the first positive edge of the clock after this line

goes HIGH. This point is indicated by the cursor line on the transition from channel 1

to channel 2.

The circuit in Figure 12.44 could be expanded to convert all eight analog channels

from the ADC, but the chosen CPLD (EPM7128SLC84) does not have enough I/O pins.

Eight 8-bit latch outputs require 64 pins; the CPLD only has 60 user I/Os. An 8-channel

system could be implemented if it used eight external latches, such as eight 74HC373 octal

latches, or internal latches on a different CPLD. Note that the CPLD has enough logic

cells to implement the system, just not enough I/O pins. The identical device in a different

package (EPM7128SQC100; 100-pin quad flat-pack) can accommodate the entire

system.

to a 3-line-to-8-line device.

Summary 613

FIGURE 12.46

Simulation of 4-channel Data Acquisition System

❘❙❚ SECTION 12.4 REVIEW PROBLEM

12.8 Calculate the highest-frequency component of an analog signal that can be accurately

converted by the 4-channel data acquisition system in Figure 12.44. Assume the system

clock is running at 787 kHz.

S U M M A R Y

01. An analog system can represent a physical property (e.g.,

temperature, pressure, or velocity) by a proportional voltage

or current. The mathematical function describing the

analog voltage or current is continuous throughout a defined

range.

of binary numbers of a fixed bit size.

03. Digital representations of data are not subject to the same

distortions as analog representations. They are also easier to

store and reproduce than analog.

04. The quality of a digital representation depends on the sampling

frequency and quantization (number of bits) of the system

that converts an analog input to a digital output.

05. The resolution of a system is a function of the number of bits

in its digital representation. A greater number of bits implies

that the sampled analog input can be broken up into more,

smaller segments, allowing each segment to more closely approximate

the original input value.

06. A digital-to-analog converter (DAC) uses electronic switches

to sum binary-weighted currents to a total analog output current.

Analog current can be calculated by:

or, more simply:

for an n-bit DAC, where bn_1bn_2… b2b1b0 is the digital

input code,

and

scale) current.

07. The maximum output of a DAC is full scale (FS) minus

the value represented by a change in the least significant

bit of the input (FS _ 1 LSB). For example, for a 4-bit

converter (1 LSB _ 1/16 FS), the maximum output is (FS

_ 1/16 FS) _ 15/16 FS. For an 8-bit converter (1 LSB _

1/256 FS), the maximum output is (FS _ 1/256 FS) _

255/256 FS.

Ia n I digital code

ref 2

______

08. A weighted-resistor DAC derives its binary-weighted currents

from binary-weighted resistors connected to the reference

voltage supply.

09. An R-2R ladder DAC derives its binary weighted currents

from a resistor ladder network that consists of resistors of

two values only, one of which is twice the other. The R-2R

ladder is more common than the weighted resistor DAC.

10. A DAC input code consisting of a 1 followed by all 0s represents

an output of _1

2

_ FS, regardless of the number of bits in

output of _1

4

_ FS. A code of 11 followed by all 0s is _3

_ FS.

11. The MC1408 DAC is an example of a monolithic (singlechip)

DAC. Output current at pin 4 is a binary-weighted fraction

of the reference current at pin 14:

12. If the output of an MC1408 DAC is buffered by an noninverting

op amp with a feedback resistance of RF, the output

voltage is given by:

13. An 8-bit DAC can be used as a ramp generator by connecting

an 8-bit binary counter to the digital inputs.

14. An MC1408 DAC can be configured for bipolar output by

connecting a pull-up resistor (R4) from the output (pin 4) to

the reference voltage supply. Output is given by:

15. A DAC is monotonic if every increase in binary input results

in an increase in analog output.

16. DAC errors include: offset error (nonzero output for zero input

code), gain error (output falling above or below FS _

1LSB for maximum input code due to an incorrect slope),

linearity error (deviation from straight-line approximation

between codes), and differential nonlinearity (deviation of

step sizes from ideal of one step per LSB).

17. DAC linearity error of greater than __1

2

_ LSB can result in a

18. Several popular types of analog-to-digital converters (ADC)

are flash or simultaneous, successive approximation, and

dual slope or integrating.

19. AflashADCconsistsof avoltage divider with thesamenumber

of steps as output codes, a set of comparators (onefor every output

code), and a priority encoder.All comparators whose reference

input is less than the analog input will fire, the priority encoder

will detect the highest-value active comparator, and

generate the corresponding output code. A flash ADC is fast,

but requires 2n comparators for an n-bit output code.

20. An ADC transfer characteristic is set up so that all codes are

1 LSB wide, except for the first and last codes. The code for

0 is _1

_ LSB wide and the maximum code is 1_1

2

_ LSB wide. This

of the code’s range of analog input values.

21. A successive approximation ADC consists of a state machine

called a successive approximation register (SAR) whose bits









256 14

4

ref









256 14









256

14

can be set and cleared individually in a specific sequence, a

22. A successive approximation ADC sets each bit of the SAR in

turn as an approximation of the required digital code. For

each bit, the approximation is converted back to analog form

and compared with the incoming analog value. If the converted

value is less than the actual analog value, the bit remains

set and the next bit is tried. If the converted value is

greater than the actual analog input, the bit is cleared and the

next bit is tried.

23. A dual slope ADC consists of an integrator, comparator,

counter, and control logic. The integrator output changes

with a slope of _Vin/RC for a constant input. This ADC allows

the integrator to charge for the time required for the

counter to complete one full cycle (known time). At that

time, the integrator input is switched to a reference voltage of

opposite polarity. The reference voltage discharges the integrator

at a known rate. The time required to do this is stored

in the counter and represents the fraction of full scale analog

voltage applied to the converter.

24. A sample and hold circuit may be required to hold the input

value of an ADC constant for the conversion time of the

ADC. It samples an analog signal at periodic intervals and

holds the sampled value in a capacitor until the next sample

is taken. A track and hold circuit performs a similar function,

but allows the capacitor to charge and discharge along with

the changing analog signal, holding its value only during the

conversion time of the ADC.

25. In order to preserve the information in an analog signal, it

must be sampled at a frequency of at least twice the maximum-

frequency component of the signal (fs fmax). This criterion

is called the Nyquist sampling theorem.

26. If the Nyquist sampling theorem is violated, an alias frequency,

or false low-frequency component, will be added to

the digital representation of the analog signal.

27. Alias frequencies can be eliminated with an anti-aliasing filter,

a low-pass filter used to pass only frequencies less than

2fs to the input of an ADC. This input frequency range automatically

satisfies the Nyquist criterion at the ADC input.

28. An ADC0808 successive approximation ADC contains an

8-channel analog MUX and can be used as the basis for an

8-channel data acquisition system.

29. The conversion sequence for the ADC0808 is as follows:

appropriate address on lines ADD C, ADD B, and

clock cycles _2 _s after START.

output.

machine.

octal latch for each analog channel, a state-machine controller,

and a counter/decoder circuit to select the active analog

channel and latch.

Problems 615

G L O S S A R Y

component in a sampled analog signal due to a sampling

frequency that is too slow relative to the sampled analog

signal.

of twice the maximum frequency of a sampled signal, used to

prevent aliasing in an ADC.

Analog A way of representing some physical quantity, such as

temperature or velocity, by a proportional continuous voltage or

current. An analog voltage or current can have any value within

a defined range.

signal at its input to a digital code. (Also called an A-to-D converter,

A/D converter, or ADC.)

Continuous Smoothly connected. An unbroken series of consecutive

values with no instantaneous changes.

data from several analog sources.

of binary numbers. A digital representation can have only specific

discrete values.

Digital-to-analog converter A circuit that converts a digital

code at its input to an analog voltage or current. (Also called a

D-to-A converter, D/A converter, or DAC.)