1.12 REFERENCES
REFERENCES
J. Sack and J: Meadows, Entering BASIC, Science Research Associates, 1973.
C. Pegels, BASIC: A Computer Programming Language, Holden-Day, Inc., 1973.
J. Kemeny and T. Kurtz, BASIC Programming, People Computer Company, 1967.
Albrecht, Finkle, and Brown, BASIC, People Computer Company, 1973.
T. Dwyer, A Guided Tour of Computer Programming in BASIC, Houghton Mifflin Co., 1973.
Eugene H. Barnett, Programming Time Shared Computers in BASIC, Wiley-Interscience, L/C 72-175789.
Programming Language #2, Digital Equipment Corp., Maynard, Mass. 01754.
101 BASIC Computer Games, Digital Equipment Corp., Maynard, Mass. 01754.
What to do After You Hit Return. People Computer Company.
BASIC-80 REFERENCE MANUAL, Intel Corp., Santa Clara, Calif
APPEENDIX B
INSTRUCTION SET SUMMARY
This appendix contains two tables (see tables B-1 and B-2): the first identifies all of the 8052's instructions in alphabetical order; the second table lists the instructions according to their hexadecimal opcodes and lists the assembly language instructions that produced that opcode.
The alphabetical listing also includes documentation of the bit pattern, flags affected, number of machine cycles per execution and a description of the instructions operation and function. The list below defines the conventions used to identify operation and bit patterns.
ABBREVIATIONS AND NOTATIONS USED
A
|
Accumulator
|
|
11111111
|
One byte of a 16-bit address encoded in operand byte
|
AB
|
Register Pair
|
mmmmmmmm
|
Data address encoded in operand byte
|
B
|
Multiplication Register
|
oooooooo
|
Relative offset encoded in operand byte
|
bit address
|
8052 bit address
|
r or rrr
|
Register identifier encoded in operand byte
|
page address
|
11-bit code address within 2K page
|
AND
|
Logical AND
|
relative offset
|
8-bit 2's complement offset
|
NOT
|
Logical complement
|
C
|
Carry Flag
|
OR
|
Logical OR
|
code address
|
Absolute code address
|
XOR
|
Logical exclusive OR
|
data
|
Immediate data
|
+
|
Plus
|
data address
|
On-chip 8-bit RAM address
|
-
|
Minus
|
DPTR
|
Data pointer
|
/
|
Divide
|
PC
|
Program Counter
|
-
|
Multiply
|
Rr
|
Register (r=0-7)
|
(X)
|
The contents of X
|
SP
|
Stack pointer
|
((X))
|
The memory location addressed by (X) (The contents of X)
|
high
|
High order byte
|
=
|
Is equal to
|
low
|
Low order byte
|
<>
|
Is not equal to
|
i-j
|
Bits i through j
|
<
|
Is less than
|
.n
|
Bit n
|
>
|
Is greater than
|
aaa aaaaaaaa
|
Absolute page address encoded in instruction and operand byte
|
<-
|
Is replaced by
|
bbbbbbbb
|
Bit address encoded in operand byte
|
|
|
dddddddd
|
Immediate data encoded in operand byte
|
|
|
Table B-1. Instruction Set Summary
Mnemonic Operation
|
Cycles
|
Binary Code
|
Flags
P OV AC C
|
Function
|
ACALL code addr
(PC) <- (PC)+2
(SP) <- (SP)+1
((SP))<-(PC) low
(SP)<-(SP)+1
((SP))<-(PC) high
(PC) 0-10<-page address
|
2
|
a a a 1 0 0 0 1
a a a a a a a a
|
P OV AC C
|
Push PC on stack, and replace low order 11 bits with low order 11 bits of code address.
|
ADD A,#data
(A)<-(A)+data
|
1
|
0 0 1 0 0 1 0 0
d d d d d d d d
|
P OV AC C
|
Add immediate data to A.
|
ADD A,@Rr
(A)<-(A)+((Rr))
|
1
|
0 0 1 0 0 1 1 r
|
P OV AC C
|
Add contents of indirect address to A.
|
ADD A,Rr
(A)<-(A)+(Rr)
|
1
|
0 0 1 0 1 r r r
|
P OV AC C
|
Add register to A.
|
ADD A,data addr
(A)<-(A)+(data address)
|
1
|
0 0 1 0 0 1 0 1
m m m m m m m m
|
P OV AC C
|
Add contents of data address to A.
|
ADDC A,#data
(A)<-(A)+(C)+data
|
1
|
0 0 1 1 0 1 0 0
d d d d d d d d
|
P OV AC C
|
Add C and immediate data to A
|
ADDC A,@Rr
(A)<-(A)+(C)+((Rr))
|
1
|
0 0 1 1 0 1 1 r
|
P OV AC C
|
Add C and contents of indirect address to A.
|
ADDC A,Rr
(A)<-(A)+(C)+(Rr)
|
1
|
0 0 1 1 1 r r r
|
P OV AC C
|
Add C and register to A
|
ADDC A,data addr
(A)<-(A)+(C)+(data address)
|
1
|
0 0 1 1 0 1 0 1
m m m m m m m m
|
P OV AC C
|
Add C and contents of data address to A
|
AJMP code addr
(PC) 0-10<-code address
|
2
|
a a a 0 0 0 0 1
a a a a a a a a
|
|
Replace low order 11 bits of PC with low order 11 bits code address.
|
ANL A,#data
(A)<-(A)AND data
|
1
|
0 1 0 1 0 1 0 0
d d d d d d d d
|
P
|
Logical AND immediate data to A.
|
ANL A,@Rr
(A)<-(A) AND ((Rr))
|
1
|
0 1 0 1 0 1 1 r
|
P
|
Logical AND contents of indirect address to A
|
ANL A,Rr
(A)<-(A) AND (Rr)
|
1
|
0 1 0 1 1 r r r
|
P
|
Logical AND register to A
|
ANL A,data addr
(A)<-(A) AND (data address)
|
1
|
0 1 0 1 0 1 0 1
m m m m m m m m
|
P
|
Logical AND contents of data address to A.
|
ANL C,bit addr
(C)<-(C) AND (bit address)
|
2
|
1 0 0 0 0 0 1 0
b b b b b b b b
|
C
|
Logical AND bit to C
|
ANL C,lbit addr
(C)<-(C) AND NOT (bit address)
|
2
|
1 0 1 1 0 0 0 0
b b b b b b b b
|
C
|
Logical AND complement of bit to C
|
ANL data addr, #data
(data address)<-
(data address) AND data
|
2
|
0 1 0 1 0 0 1 1
m m m m m m m m
d d d d d d d d
|
|
Logical AND immediate data to contents of data address
|
ANL data addr,A
(data address)<-
(data address) AND A
|
1
|
0 1 0 1 0 0 1 0
m m m m m m m m
|
|
Logical AND A to contents of data address.
|
Table B-1. Instruction Set Summary (Cont'd.)
Mnemonic Operation
|
Cycles
|
Binary Code
|
Flags
P OV AC C
|
Function
|
CJNE @Rr,#data,code addr
(PC)<- (PC)+3
IF ((Rr))<> data
THEN
(PC)<-(PC)+relative offset
IF ((Rr))
ELSE(C)<-0
|
2
|
1 0 1 1 0 1 1 r
d d d d d d d d
o o o o o o o o
|
C
|
If immediate data and contents of indirect address are not equal, jump to code address.
|
CJNE A,#data,code addr
(PC)<-(PC)+3
IF(A)<>data
THEN
(PC)<-(PC)+relative offset
IF (A)
ELSE(C)<-0
|
2
|
1 0 1 1 0 1 0 0
d d d d d d d d
o o o o o o o o
|
C
|
If immediate data and A are not equal, jump to code address.
|
CJNE A,data addr,code addr
(PC)<-(PC)+3
IF (A)<>(data address)
THEN
(PC)<-(PC)+relative offset
IF (A)<(data address) THEN(C)<-1
ELSE(C)<-0
|
2
|
1 0 1 1 0 1 0 1
m m m m m m m m
o o o o o o o o
|
C
|
If contents of data address and A are not equal, jump to code address.
|
CJNE Rr,#data,code addr
(PC)<-(PC)+3
IF (Rr)<>data
THEN
(PC)<-(PC)+relative offset
IF (Rr)
THEN(C)<-1
ELSE(C)<-0
|
2
|
1 0 1 1 1 r r r
d d d d d d d d
o o o o o o o o
|
C
|
If immediate data and register are not equal, jump to code address.
|
CLR A
(A)<-0
|
1
|
1 1 1 0 0 1 0 0
|
P
|
Set A to zero(O).
|
CLR C
(C)<-0
|
1
|
1 1 0 0 0 0 1 1
|
C
|
Set C to zero (0).
|
CLR bit addr
(bit address)<-0
|
1
|
1 1 0 0 0 0 1 0
b b b b b b b b
|
|
Set bit to zero (0).
|
CPL A
(A)<-NOT (A)
|
1
|
1 1 1 1 0 1 0 0
|
P
|
Complements each bit in A.
|
CPL C
(C)<-NOT (C)
|
1
|
1 0 1 1 0 0 1 1
|
C
|
Complement C.
|
CPL bit addr
(bitaddress)<-NOT (bit address)
|
1
|
1 0 1 1 0 0 1 0
b b b b b b b b
|
|
Complement bit.
|
DA A
|
1
|
1 1 0 1 0 1 0 0
|
P C
|
Adjust A after a BCD add.
|
DEC @Rr
((Rr))<-((Rr))-1
|
1
|
0 0 0 1 0 1 1 r
|
|
Decrement contents of indirect address.
|
DEC A
(A)<-(A)-1
|
1
|
0 0 0 1 0 1 0 0
|
P
|
Decrement A.
|
DEC Rr
(Rr)<-(Rr) -1
|
1
|
0 0 0 1 1 r r r
|
|
Decrement register.
|
Table B-1. Instruction Set Summary (Cont'd.)
Mnemonic Operation
|
Cycles
|
Binary Code
|
Flags
P OV AC C
|
Function
|
DEC data addr
(data address)<-
(data address)-1
|
1
|
0 0 0 1 0 1 0 1
m m m m m m m m
|
|
Decrement contents of data address.
|
DIV AB
(AB)<-(AJ/(B)
|
4
|
1 0 0 0 0 1 0 0
|
P OV C
|
Divide A by B (multiplication register).
|
DJNZ Rr,code addr
(PC)<-(PC)+2
(Rr)<-(Rr)-1
IF(Rr)<>0
THEN
(PC)<-(PC)+relative offset
|
2
|
1 1 0 1 1 r r r
o o o o o o o o
|
|
Decrement register, if not zero (0), then jump to code address.
|
DJNZ data addr,code addr
(PC),<-(PC)+3
(data address)<-(
(data address)-1
IF (data address)<>0
THEN
(PC)<-(PC)+relative offset
|
2
|
1 1 0 1 0 1 0 1
m m m m m m m m
o o o o o o o o
|
|
Decrement data address, if zero (0), then jump to code address.
|
INC @Rr
((Rr))<-((Rr))+1
|
1
|
0 0 0 0 0 1 1 r
|
|
Increment contents of indirect address.
|
INC A
(A)<-(A)+1
|
1
|
0 0 0 0 0 1 0 0
|
P
|
Increment A.
|
INC DPTR
(DPTR)<-(DPTR)+1
|
1
|
1 0 1 0 0 0 1 1
|
|
Increment 16-bit data pointer.
|
INC Rr
((R)<-(Rr)+1
|
1
|
0 0 0 0 1 r r r
|
|
Increment register.
|
INC data addr
(data address)<-
(data address)+1
|
2
|
0 0 0 0 0 1 0 1
m m m m m m m m
|
|
Increment contents of data address.
|
JB bit addr,code addr
(PC)<-(PC)+3
IF (bit address)=1
THEN
(PC)<-(PC)+relative offset
|
2
|
0 0 1 0 0 0 0 0
b b b b b b b b
o o o o o o o o
|
|
If bit is one, n jump to code address.
|
JBC bit addr,code addr
(PC)<-(PC)+3
IF (bit address)=1
THEN
(bit address)<-0
(PC)<-(PC)+relative offset
|
2
|
0 0 0 1 0 0 0 0
b b b b b b b b
o o o o o o o o
|
|
If bit is one, n clear bit and jump to code address.
|
JC code addr
(PC) (PC)+2
IF(C)=1
THEN
(PC)<-(PC)+relative offset
|
2
|
0 1 0 0 0 0 0 0
o o o o o o o o
|
|
If C is one, then jump to code address.
|
JMP @A+DPTR
(PC)<-(A)+(DPTR)
|
2
|
0 1 1 1 0 0 1 1
|
|
Add A to data pointer and jump to that code address.
|
JNB bit addr,code addr
(PC)<-(PC)+3
IF (bit address)=0
THEN
(PC)<-(PC)+relative offset
|
2
|
0 0 1 1 0 0 0 0
b b b b b b b b
o o o o o o o o
|
|
If bit is zero, n jump to code address.
|
Table B-1. Instruction Set Summary (Cont'd.)
Mnemonic Operation
|
Cycles
|
Binary Code
|
Flags
P OV AC C
|
Function
|
JNC code addr
(PC)+(PC)+2
IF (C)=0
THEN
(PC)<-(PC)+relative offset
|
2
|
0 1 0 1 0 0 0 0
o o o o o o o o
|
|
If C is zero (0), n jump to code address.
|
JNZ code addr
(PC)<-(PC)+2
IF (A)<>0
THEN
(PC)<-(PC)+relative offset
|
2
|
0 1 1 1 0 0 0 0
o o o o o o o o
|
|
If A is not zero (0), n jump to code address.
|
JZ code addr
(PC)<-(PC)+2
IF (A)=0
THEN
(PC)<-(PC)+relative offset
|
2
|
0 1 1 0 0 0 0 0
o o o o o o o o
|
|
If A is zero (0), then jump to code address.
|
LCALL code addr
(PC)<-(PC)+3
(SP)<-(SP)+1
((SP))<-((PC)) low
(SP)<-(SP)+1
((SP))<-(PC) high
(PC)<-code address
|
2
|
0 0 0 1 0 0 1 0
1 1 1 1 1 1 1 1 +
1 1 1 1 1 1 1 1 +
|
|
Push PC on stack and replace entire PC value with code address.
|
LJMP code addr
(PC)<-code address
|
2
|
0 0 0 0 0 0 1 0
1 1 1 1 1 1 1 1 +
1 1 1 1 1 1 1 1 +
|
|
Jump to code address.
|
MOV @Rr,#data
((Rr))<-data
|
1
|
0 1 1 1 0 1 1 r
d d d d d d d d
|
|
Move immediate data to indirect address.
|
MOV @Rr,A
((Rr)) <-(A)
|
1
|
1 1 1 1 0 1 1 r
|
|
Move A to indirect address.
|
MOV @Rr,data addr
((Rr))<-(data address)
|
2
|
1 0 1 0 0 1 1 r
m m m m m m m m
|
|
Move contents of data address to indirect address.
|
MOV A,#data
(A)<-data
|
1
|
0 1 1 1 0 1 0 0
d d d d d d d d
|
P
|
Move immediate data to A.
|
MOV A,@Rr
(A) -< ((Rr))
|
1
|
1 1 1 0 0 1 1 r
|
P
|
Move contents of indirect address to A.
|
MOV A,Rr
(A)<-(Rr)
|
1
|
1 1 1 0 1 r r r
|
P
|
Move register to A.
|
MOV A,data addr
(A)<-(data address)
|
1
|
1 1 1 0 0 1 0 1
m m m m m m m m
|
P
|
Move contents of data address to A.
|
MOV C,bit addr
(C)<-(bitaddress)
|
1
|
1 0 1 0 0 0 1 0
b b b b b b b b
|
C.
|
Move bit to C
|
MOV DPTR,#data
(DPTR)<-data
|
2
|
1 0 0 1 0 0 0 0
d d d d d d d d +
d d d d d d d d +
|
|
Move two bytes of immediate data pointer.
|
MOV Rr,#data
(Rr)<-data
|
1
|
0 1 1 1 1 r r r
d d d d d d d d
|
|
Move immediate data to register.
|
MOV Rr,A
(Rr)<-(A)
|
1
|
1 1 1 1 1 r r r
|
|
Move A to register.
|
+ The high order byte of the 16-bit operand is in the first byte following the opcode. The low order byte is in the second byte following the opcode.
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