Vlsi design lab (EC16203) session 2020-2021

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MOD 13 counter 20185100962

PRAYAGRAJ, INDIA- 211004
Conclusion

VLSI DESIGN LAB (EC16203) SESSION 2020-2021

LAB REPORT SUBMITTED BY

RAVI KUMAR VERMA (20185012)

ECE 3

DEPARTMENT OF ELECTR ONICS AND COMMUNICATION ENGINEERIN G MOTILAL NEHRU NATION AL INSTITUTE OF TECHNOLOGY ALLAHABAD

PRAYAGRAJ, INDIA- 211004

DATE: 01/02/2021

Experiment- 2b
Objective- To write an HDL of 4-bit MOD 13 counter and test its operation. Tools Used – ISE Design Suit 14.7

Verilog Code –
`reg rst;
// Outputs

Verilog Code

`timescale 1ns / 1ps

module mod13 #(parameter n=13 , parameter w=4)

( input clk, input rst , output reg [w-

1:0]out); always @ (posedge clk)

begin

if(!rst)

begin

out<=0;

end else begin

if(out ==n-1)

out<=0;

else

out<=out+1;

end

end

endmodule

FOR TESTING –

`timescale 1ns / 1ps

module test;

// Inputs

reg clk;

reg rst;

// Outputswire [3:0] out;

// Instantiate the Unit Under Test

(UUT) mod13 uut (

.clk(clk),

.rst(rst),

.out(out)

);

always #50 clk=~clk;

initial begin

// Initialize

Inputs clk =

0;

rst = 0;

// Wait 100 ns for global reset to

finish #100;

rst=1;

#100;

rst=0;

// Add stimulus here

end

endmodule

Output –
RTL Schematic

F
OR TESTING-

Conclusion –

The Verilog module of 4-bit MOD 13 counter has been successfully imple mented on ISE design suite software . The RTL Schematic was generated and result have been verified and attached in output sectio n.

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