Why do we emphasize on setup violation before cts and hold violation after cts?



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http://www.vlsi-basics.com/2013/10/clock-tree-synthesis-cts.html

http://tech.tdzire.com/why-pre-cts-clock-uncertainty-value-is-more-than-post-cts/

https://blogs.cuit.columbia.edu/zp2130/clock_tree_latency_skew_uncertainty/

https://www.youtube.com/watch?v=1QPzW-WSwHo


How to write sdc for pre/post CTS ?




yamakazuover 5 years ago

I want to set different clock uncertainity values in the same sdc file for both pre and post CTS modes. Can I do that ? The following sdc didn't work. How to do that ?

if {[getAnalysisMode -clockPropagation -quiet] == "forcedIdeal"} {
    set jit_add 0.2
} else {
    set jit_add 0
}
set_clock_uncertainty [expr 0.200+${jit_add}] \
  -from [get_clocks {my_clk}] -to [get_clocks {my_clk}]

Why do we emphasize on setup violation before CTS and hold violation after CTS?

Setup time of a valid timing path depends on : Max data network computation time vs clock edge arrival time at the sink.Until POST CTS stage, we assume all clocks as ideal networks and it could reach in 0 time to every possible clock sink of the chip!!What we need to focus is in implementing the data path in such a way that it should at least not take more than one single clock period of the clock from start point to end point. (assuming a full cycle valid timing path).And out of the two components of the setup timing check, one is always a constant (time period of the clock) and the other variable is data path delay which we have all the options to play with till CTS stage completes. If we can’t meet this stretch goal before CTS, there is going to be a hard time in closing the timing later. Hence until CTS stage, we focus on getting data path synthesis or data network physical implementation alone

I hope it is clear why we focus on setup timing before CTS stage.

Let’s see in the other view, why don’t we just focus on hold time ?



Hold time of a path depends on : minimum data path delay vs clock edge time. Since Clock reaches in zero time every sink of the chip and at the minimum, data path delay will be always greater than the hold req of a flop/timing path end point. So that’s it, unless if there is going to be a change in the clock path network delay, there is no point of analyzing hold timing of a valid path right ? ( But at bare minimum, one can review the gross hold timing paths just to see if it’s a FP/MCP.)
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