Chapter 1 Basic Principles of Digital Systems outlin e 1
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3.12 Find the Boolean expression, in both sum-of-products (SOP) and product-of-sums (POS) forms, for the logic function represented by the following truth table. Draw the logic diagram for the SOP form only. Problems 109 tion.
Section 3.3 Theorems of Boolean Algebra 3.17 Write the Boolean expression for the circuit shown in Figure 3.65 Use the distributive property to transform the circuit into a sum-of-products (SOP) circuit.
Figure 3.66 Use the distributive property to transform the circuit into a sum-of-products (SOP) circuit.
expressions as much as possible. a. Y _ A A B _ C A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 A B C D Y FIGURE 3.65 Problem 3.17 Logic Circuit
the logic diagram of the POS form of the XOR function. 3.16 Write the POS form of the 2-input XNOR function. Draw the logic diagram of the POS form of the XNOR func- FIGURE 3.66 Problem 3.18 Logic Circuit A B C D E F A B C Y 0 0 0 0
0 0 1 1 0 1 0 0
0 1 1 1 1 0 0 0
1 0 1 1 1 1 0 0
1 1 1 1 A B C Y 0 0 0 1
0 0 1 0 0 1 0 1
0 1 1 0 1 0 0 0
1 0 1 0 1 1 0 1
1 1 1 0 b. Y _ A A_ B _ C c. J _ K _ L L_ d. S _ (T _ U) V V_ e. S _ T _ V V_ f. Y _ (A B_ _ C_)(B D_ _ F) 3.20 Use the rules of Boolean algebra to simplify the following expressions as much as possible. a. M _ P Q _ P__Q_ R b. M _ P Q _ P Q R c. S _ (T_____U_) V _ (T _ U) d. Y _ (A_ _ B _ D_) A C _ A B_ D e. Y _ (A_ _ B _ D_) A C _ A B_ D f. P _ (Q__R_ _ S T )(Q__R_ _ Q) g. U _ (X _ Y_ _ W_ Z)(W Y _Y _ W_ Z) 3.21 Use the rules of Boolean algebra to simplify the following expressions as much as possible. a. Y _ A__B_ C D _ (A_ _ B_) C_____D_ _ A_ _ B_ b. Y _ A__B_ C D _ (A_ _ B_) C_____D_ _ A_ _ B_ c. K _ (L_ M _ L M_)(M N_ _ L M N) _ M(N_ _ L) Section 3.4 Simplifying SOP and POS Expressions 3.22 Use the rules of Boolean algebra to find the maximum SOP and POS simplifications of the function represented by the following truth table.
SOP and POS simplifications of the function represented by the following truth table.
SOP and POS simplifications of the function represented by the following truth table.
SOP simplification of the function represented by the following truth table.
SOP simplification of the function represented by the following truth table.
0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0
0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0
SOP simplification of the function represented by the following truth table.
0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1
SOP simplification of the function represented by the following truth table.
0 0 0 0
0 0 1 1 0 1 0 0
0 1 1 1 1 0 0 0
1 0 1 1 1 1 0 0
1 1 1 0 A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1
SOP simplification of the function represented by the following truth table. Problems 111 3.35 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form.
Method
3.31 Use the Karnaugh map method to find the maximum SOP A B C D Y 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 simplification of the logic diagram in Figure 3.21. 3.32 Use the Karnaugh map method to reduce the following Boolean expressions to their maximum SOP simplifications: a. Y _ A_ B_ C _ A_ B C _ A B C b. Y _ A_ B_ C _ A_ B C _ A B C_ _ A B C _ A B_ C c. Y _ A_ B_ C_ _ A_ B C _ A B C _ A B_ C d. Y _ A_ B_ C_ D_ _ A_ B_ C_ D _ A_ B_ C D _ A_ B_ C D_ _ A_ B C D_ _ A B C_ D _ A B C D_ _ A B_ C_ D_ _ A B_ C D_
represented by the following truth table to simplest SOP form.
represented by the following truth table to simplest SOP form.
0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X
represented by the following truth table to simplest SOP form.
SOP simplification of the function represented by the following truth table.
represented by the following truth table to simplest SOP form.
represented by the following truth table to simplest SOP form.
0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1
represented by the following truth table to simplest SOP form.
0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1
represented by the following truth table to simplest SOP form.
0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0
represented by the following truth table to simplest SOP form.
0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 Problems 113 3.42 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form.
Example 3.22. Use a similar design procedure to develop A B C D Y 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1
0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0
represented by the following truth table to simplest SOP form.
0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 simplification. FIGURE 3.67 Problem 3.44: Logic Circuit
Problem 3.45: Logic Circuit the circuit of a 2421-to-BCD code converter. 3.47 Excess-3 code is a decimal code that is generated by adding 0011 (_ 310) to a BCD code. Table 3.18 shows 3.44 The circuit in Figure 3.67 represents the maximum SOP simplification of a Boolean function. Use a Karnaugh map to derive the circuit for the maximum POS
A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S
POS: Y _ (A _ B _ C)(A _ B _ C_)(A _ B_ _ C) (A _ B_ _ C_)(A_ _ B_ _ C)(A_ _ B_ _ C_)
POS: Y _ (A _ B _ C_)(A _ B_ _ C)(A _ B_ _ C_) (A_ _ B_ _ C_)
0 0 0 0
0 0 1 1 0 1 0 1
0 1 1 1 1 0 0 0
1 0 1 1 1 1 0 0
1 1 1 0 Table 3.18 BCD and Excess-3 Code Decimal BCD Code Excess-3 Equivalent D4 D3 D2 D1 E4 E3 E2 E1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 2 0 0 1 0 0 1 0 1 3 0 0 1 1 0 1 1 0 4 0 1 0 0 0 1 1 1 5 0 1 0 1 1 0 0 0 6 0 1 1 0 1 0 0 1 7 0 1 1 1 1 0 1 0 8 1 0 0 0 1 0 1 1 9 1 0 0 1 1 1 0 0 the relationship between a decimal digital code, natural BCD code, and Excess-3 code. Draw the circuit of a BCD-to-Excess-3 code converter, using the Karnaugh map method to simplify all Boolean expressions.
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Introduction to PLDs and MAX_PLUS II O U T L I N E 4.1 What is a PLD? 4.2 Programming PLDs using MAX_PLUS II 4.3 Graphic Design File 4.4 Compiling MAX_PLUS II Files 4.5 Hierarchical Design 4.6 Text Design File (VHDL)
4.7 Creating a Physical Design
C H A P T E R O B J E C T I V E S Upon successful completion of this chapter you will be able to: • Describe some advantages of programmable logic over fixed-function logic.
• Name some types of programmable logic devices (PLDs). • Use Altera’s MAX_PLUS II PLD Design Software to enter simple combinational circuits using schematic capture. • Use VHDL entity declarations, architecture bodies, and concurrent signal assignments to enter simple combinational circuits. • Create circuit symbols from schematic or VHDL designs and use them in hierarchical designs for PLDs. • Assign device and pin numbers to schematic or VHDL designs and compile them for programming Altera MAX7000S or FLEX10K20 devices. • Program Altera PLDs via a JTAG interface and a ByteBlaster Parallel Port Download Cable. In the first three chapters of this book, we examined logic gates and Boolean algebra. These basic foundations of combinational circuitry, as well as the sequential logic circuits we will study in a later chapter, form the fundamental building blocks of many digital integrated circuits (ICs). In the past, such digital ICs were fixed in their logic functions; it was not possible to change designs without changing the chips in a circuit. Programmable logic offers the digital circuit designer the possibility of changing design function even after it has been built. A programmable logic device (PLD) can be programmed, erased, and reprogrammed many times, allowing easier prototyping and design modification. (The industry marketing buzz often refers to “rapid prototyping” and “reduced time to market.”) The number of IC packages required to implement a design with one or more PLDs is often reduced, compared to a design fabricated using standard fixed-function ICs. PLDs can be programmed from a personal computer (PC) or workstation running special software. This software is often associated with a set of programs that allow us to design circuits for various PLDs. MAX_PLUS II, owned by Altera Corporation, is such a software package. MAX_PLUS II allows us to enter PLD designs, either as schematics or in several hardware description languages (specialized computer languages for modeling and synthesizing digital hardware). A design can contain components that are in themselves complete digital circuits. MAX_PLUS II converts the design information 116 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II into a binary form that can be transferred into a PLD via a special interface connected to the parallel port of a PC. _
by the user to implement any digital logic function. Complex PLD (CPLD) A digital device consisting of several programmable sections with internal interconnections between the sections. MAX_PLUS II CPLD design and programming software owned by Altera Corporation. Schematic capture A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD. Compile The process used by CPLD design software to interpret design information (such as a drawing or text file) and create required programming information for a CPLD. One of the most far-reaching developments in digital electronics has been the introduction of programmable logic devices (PLDs). Prior to the development of PLDs, digital circuits were constructed in various scales of integrated circuit logic, such as small scale integration (SSI) and medium scale integration (MSI) devices. These devices contained logic gates and other digital circuits. The functions were determined at the time of manufacture and could not be changed. This necessitated the manufacture of a large number of device types, requiring shelves full of data books just to describe them. Also, if a designer wanted a device with a particular function that was not in a manufacturer’s list of offerings, he or she was forced to make a circuit that used multiple devices, some of which might contain functions neither wanted nor needed, thus wasting circuit board space and design time. Programmable logic provides a solution to these problems. A PLD is supplied to the user with no logic function programmed in at all. It is up to the designer to make the PLD perform in whatever way a design requires; only those functions required by the design need be programmed. Since several functions can usually be combined in the design and programmed onto a single chip, the package count and required board space can be reduced as well. Also, if a design needs to be changed, a PLD can be reprogrammed with the new design information, often without removing it from the circuit. PLD is a generic term. There is a wide variety of PLD types, including PAL (programmable array logic), GAL (generic array logic), EPLD (erasable PLD), CPLD (complex PLD), FPGA (field-programmable gate array), as well as several others. We will be focussing on CPLDs as a representative type of PLD. Although terminology varies somewhat throughout the industry, we will use the term CPLD to mean a device with several programmable sections that are connected internally. In effect, a CPLD is several interconnected PLDs on a single chip. This structure is not apparent to the user and doesn’t really concern us at this time, except as background information. We will look at the structure of PALs, GALs, and CPLDs in Chapter 8. We will use the term “PLD” when we are referring to a generic device and “CPLD” as a more specific type of PLD. A complication in the use of programmable logic is that we must use specialized computer software to design and program our circuit. Initially, this might seem as though we are adding another level of work to the design, but when these computer techniques are mastered, it shortens the design process greatly and yields a level of flexibility not otherwise available. K E Y T E R M S Directory: uploads uploads -> 587 Return function, r i(X) r i(0) r i(1) r i(2) r i(3) 1 0 2 4 6 Thermal Station, I 2 0 1 5 6 3 0 3 5 6 10 uploads -> Department of science and humanities department of mathematics part-a questions and answers uploads -> The Case Against the nypd’s Quota-Driven ‘Broken Windows’ Policing What Is It? uploads -> For want of a nail uploads -> Ownership Models There are two different types of ownership models uploads -> Police Militarization uploads -> City of rising star regular meting thursday, july 14, 2016 uploads -> Township of winfield uploads -> Stop Militarizing Law Enforcement Act of 2014 uploads -> The Black Panther Party’s Ten-Point Program What We Want Now! Download 10.44 Mb. Share with your friends:
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