Chapter 1 Basic Principles of Digital Systems outlin e 1

The parameter LPM_SVALUE is set to 960, the decimal

equivalent of H”3C0”. Figure ANS9.55 shows the simulation

of the shift register.

CLOCK

Q1

OUTPUT

Q0

OUTPUT

OUTPUT

RESET

DFF

PRN

DFF

PRN

DFF

PRN

DFF

PRN

NOT NOT

0 0 0 0 0

1 0 0 0 0

1 1 0 0 0

1 1 1 0 0

1 1 1 1 0

1 1 1 1 1

0 1 1 1 1

0 0 1 1 1

0 0 0 1 1

0 0 0 0 1

All gates used in the decoder of Figure 9.84 remain unchanged

except those decoding the MSB/LSB pairs

(Q3Q0 and Q_3Q_0). Change these to decode Q4Q0 and

Q_4Q_0. Add two new gates to decode Q4Q_3 (2nd state) and

Q_4Q3 (7th state).

well as sequential, logic.

D2 _ Q_3Q1Q_0 _ Q2Q_1 _ Q2Q0

D1 _ Q_3Q_2Q0 _ Q3Q2Q0 _ Q1Q_0

D0 _ Q_3Q_2Q_1 _ Q3Q2Q_1 _ Q_3Q2Q1 _ Q3Q_2Q1

See Figure ANS10.3.

Answers to Selected Odd-Numbered Problems 825

q3 q2 q1 q0

AND3

AND2

AND2

AND3

AND3

AND3

AND3

NOT

NOT

OR3

OR4

CLRN

D Q

CLRN

D Q

CLRN

D Q

clk

PRN

OUTPUT

q3

OUTPUT

q2

OUTPUT

q1

OUTPUT

q0

q0

K2 _ Q_1Q0

J1 _ Q_2Q0

K1 _ Q2Q0

J0 _ Q_2Q_1 _ Q2Q1

K0 _ Q_2Q1 _ Q2Q_1

See Figure ANS10.5

10.7 D1 _ Q_1Q0in1

D0 _ Q_1i_n_1_

out1 _ Q_1Q_0i_n_1_

out2 _ Q_1Q0in1

q2 q1 q0

AND2

AND2

AND2

NOT

j2

k2

j0

k1

AND2

AND2

OR2

JKFF

j2

j1

CLRN

J Q

CLRN

J Q

PRN

CLK

q2

q2

q1

q1

q0

q0

k1

K

k0

K

See Figure ANS10.7. The circuit generates a HIGH

pulse on out1 when in1 goes LOW and a HIGH pulse on

out2 when the input goes back HIGH.

Answers to Selected Odd-Numbered Problems 827

DFF

CLRN

D Q

CLRN

D Q

INPUT

q1

q1 q0

NOT

AND3

AND2

in1

OUTPUT

OUTPUT

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY prob10_9 IS

PORT(

clk, in1 : IN STD_LOGIC;

END prob10_9;

ARCHITECTURE a OF prob10_9 IS

TYPE PULSER IS (s0, s1, s2, s3);

SIGNAL sequence: PULSER;

BEGIN

BEGIN

CASE sequence IS

WHEN s0 =>

IF in1 = ‘1’ THEN

sequence <= s0; — — no change if in1 = 1

out1 <= ‘0’;

out2 <= ‘0’;

ELSE

out1 <= ‘1’; —— pulse on out1

out2 <= ‘0’;

END IF;

IF in1 = ‘0’ THEN

sequence <= s1; — — outputs LOW

out1 <= ‘0’;

out2 <= ‘0’;

ELSE

out1 <= ‘0’;

out2 <= ‘1’; —— pulse on out2

END IF;

sequence <= s0;

out1 <= ‘0’;

out2 <= ‘0’;

WHEN others =>

sequence <= s0;

out1 <= ‘0’;

out2 <= ‘0’;

END CASE;

END IF;

END a;

Answers to Selected Odd-Numbered Problems 829

USE ieee.std_logic_1164.ALL;

ENTITY prob10_11 IS

PORT(

sc, oe : OUT STD_LOGIC);

END prob10_11;

ARCHITECTURE a OF prob10_11 IS

TYPE ADC IS (idle, start, waiting, read);

SIGNAL state: ADC;

SIGNAL outputs: STD_LOGIC_VECTOR(1 downto 0);

BEGIN

oe <= outputs(0);

PROCESS (clk)

BEGIN

IF reset = ‘0’ THEN

state <= idle;

outputs <= “01”;

ELSE

CASE state IS

IF go = ‘0’ THEN

state <= idle;

outputs <= “01”;

ELSIF go = ‘1’ THEN

state <= start;

outputs <= “11”;

END IF;

state <= waiting;

outputs <= “01”;

WHEN waiting =>

IF eoc = ‘0’ THEN

state <= waiting;

outputs <= “01”;

ELSIF eoc = ‘1’ THEN

state <= read;

outputs <= “00”;

END IF;

FIGURE ANS10.9

830 Answers to Selected Odd-Numbered Problems

WHEN read =>

state <= idle;

outputs <= “01”;

END CASE;

END IF;

END PROCESS;

END a;

See Figure ANS 10.11.

open and a normally closed contact: one to set and

the other to reset the latch. The pushbutton on the Altera

UP-1 board has only a normally open contact.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY prob10_19 IS

PORT(

clk, in1, in2 : IN STD_LOGIC;

END prob10_19;

ARCHITECTURE a OF prob10_19 IS

TYPE STATE_TYPE IS (s0, s1, s2, s3, s4);

SIGNAL state: STATE_TYPE;

Answers to Selected Odd-Numbered Problems 831

BEGIN

PROCESS (clk)

IF clk‘EVENT AND clk = ‘1’ THEN

CASE state IS

WHEN s0 =>

state <= s1;

out1 <= ‘0’;

WHEN s1 =>

IF in1 = ‘1’ THEN

state <= s1;

out1 <= ‘0’;

ELSIF in1 = ‘0’ THEN

state <= s2;

out1 <= ‘1’;

END IF;

state <= s3;

out1 <= ‘0’;

WHEN s3 =>

state <= s4;

out1 <= ‘0’;

WHEN s4 =>

IF in2 = ‘1’ THEN

state <= s4;

out1 <= ‘0’;

ELSIF in2 = ‘0’ THEN

state <= s0;

out1 <= ‘1’;

END IF;

END IF;

END a;

driving capability; disadvantages—high power consumption,

rigid power supply requirements. CMOS: advantages—

low power consumption, high noise immunity,

flexible power supply requirements; disadvantages—

low output current ECL: advantages—high speed;

disadvantages—high susceptibility to noise, high power

consumption.

16 ns _ 15 ns _ 31 ns. Transition from state 2 to state 3:

tp _ tpLH00 _ 15 ns (Assume VCC _ 4.5 volts; T _ 25°C

to _55°C)

Load gate (74S32): IIL__2 mA; IIH _ 20 _A

nL _ IOL/IIL _ 8 mA/2 mA _ 4

nH _ IOH/IIH _ 0.4 mA/0.02 mA _ 20

n _ nL _ 4

11.9 Source: IOH__0.14 mA; sink: IOL _ 2.8 mA

11.11 a. 44 mW;

b. 39 mW;

c. 29 mW;

d. 20 mW

go,eoc/sc,oe

X X /00

X 1 /01

XX/00

1X/00

read start

waiting2 waiting1

idle

output voltages of VOH _ 2.7 V and VOL _ 0.8 V. The inputs

of a 74HCT series gate are voltage compatible with

LSTTL outputs since VIH _ 2 V and VIL _ 0.5V. This is

not the case for 74HC series gates, where VIH _ 3.15V

and VIL _ 1.35V. The 74LS gate is not guaranteed to

drive the 74HC gate in the HIGH state.

11.19 10 loads, since the 74HC output voltages are defined for

an output current of 4mA.

reverse-biased. Current flows, by default, through the

base-collector junction of Q1, supplying base current to

Q2, saturating it. This in turn, saturates Q3, making its

collector LOW.

LOW input: Current has a path to ground via the

base-emitter junction of Q1. This transports charge away

from the base region of Q2, making it cutoff. Since Q2 is

cutoff, no base current flows in Q3. If an external pull-up

resistor is connected to the collector of Q3, the output will

be HIGH. Otherwise, it is floating.

11.23 See Figure 11.31 in text. Y _A_B_ _ C_D_ _ E_F_ _

A_B_____C_D_____E_F_

there will be a direct connection from the output to VCC.

Since there is relatively little resistance in the current

path, the current will likely exceed the rated output current,

IOL.

11.29 a. Q3 and Q4 are never on at the same time because the

phase splitter, Q2, keeps them in opposite states. The

voltage in the circuit is divided such that when Q2 is

on, it pulls the base of Q4 into the cutoff region for

that transistor. At the same time, Q3 is supplied with

base current and thus saturated. When Q2 is off, there

is no base current in Q3, making it cutoff. The base

voltage at Q4 is now such that it is on.

the HIGH output transistor, Q4, can switch on

faster than the LOW output transistor, Q3, can switch

off. For a brief time, both transistors are on, causing a

supply current spike. This can be counteracted by connecting

a small capacitor between the supply voltage,

VCC, and ground.

11.31 7.58 mA, 95% of IOL; 2.12 mA, 530% of IOH The first

circuit is more suitable, as it can drive a higher current to

the LED and still remain within the output specification

of the inverter.

Work only on an antistaticwork surface and wear a conductive

wrist strap. Connect all unused device inputs to power

or ground.Donot touch the pins of theMOSdevice.

Answers to Selected Odd-Numbered Problems 833

11.35 See Figure 11.56 in text.

A B Q1 Q2 Q3 Q4 Q5 Q6 Y

0 0 ON ON OFF OFF OFF ON 0

0 1 OFF ON OFF ON OFF ON 0

1 0 ON OFF ON OFF OFF ON 0

1 1 OFF OFF ON ON ON ONN 1

11.37 The state of flip-flop output Q selects which signal is

switched to the data converter/display driver by enabling

one of the CMOS transmission gates. When Q_1, the

wheel rotation sensor is selected. Q_0 selects the engine

rotation sensor.

11.39 No. TTL power dissipation, and therefore the speedpower

product, depends on the logic states of the device

outputs, not on frequency.

11.41 74HCNN: pin replacement for TTL device; CMOS-compatible

inputs; TTL-compatible outputs. 74HC4NNN:

pin replacement for CMOS device; CMOS-compatible

inputs; TTL-compatible outputs. 74HCTNN: pin replacement

for TTL device; TTL-compatible inputs;

TTL-compatible outputs. 74HCUNN: unbuffered CMOS

outputs.

Chapter 12

12.1

12.5 6 bits, since 64 _ 26. Resolution _ 500 mV/64 _ 7.8125

mV.

codes.)

are the same in the first four bits. The additional

bit in the lower 4 bits adds an extra voltage to the analog

output.

8 k_, 16 k_, 32 k_, 64 k_, 128 k_, 256 k_, 512 k_,

1024 k_, 2048 k_, 4096 k_, 8192 k_, 16,384 k_,

32,768 k_. All resistors greater than 64 k_ are specified

to three or more significant figures. These values, which

are necessary to maintain conversion accuracy, are not

available as commercial components.

12.13 a. Va _ (15/16) 12 V _ 11.25 V

b. Va _ (11/16) 12 V _ 8.25 V

c. Va _ (6/16) 12 V _ 4.8 V

d. Va _ (3/16) 12 V _ 2.25 V

12.15 Resolution_(1/256)(2.2 k_12V)/6.8 k__15.16mV

12.19 There are only 16 steps in the waveform and they reach to

15/16 of the reference value. Therefore, the four least significant

bits are stuck at logic LOW.

12.21 Offset error (OE) _ 0.5 V; OE _ 0.333 LSB; OE _

4.167% FS. Gain error _ 0; Linearity error _ 0

4.375%. Gain error _ 0; Offset error _ 0

voltage to a digital code. The enable input of the latch

can be pulsed with a waveform having the same frequency

as the sampling frequency.

0 _ 0.75 000

0.75 _ 2.25 001

2.25 _ 3.75 010

3.75 _ 5.25 011

5.25 _ 6.75 100

6.75 _ 8.25 101

8.25 _ 9.75 110

9.75 _ 12.00 111

Analog Voltage Code

0.000 _ 0.375 0000

0.375 _ 1.125 0001

1.125 _ 1.875 0010

1.875 _ 2.625 0011

2.625 _ 3.375 0100

3.375 _ 4.125 0101

4.125 _ 4.875 0110

4.875 _ 5.625 0111

5.625 _ 6.375 1000

6.375 _ 7.125 1001

7.125 _ 7.875 1010

7.875 _ 8.625 1011

8.625 _ 9.375 1100

9.375 _ 10.125 1101

10.125 _ 10.875 1110

10.875 _ 12.000 1111

Fraction Sine Digital

of T Voltage Code

0 0 V 0000

T/8 4.59 V 0110

T/4 8.48 V 1011

3T/8 11.09 V 1111

T/2 12.00 V 1111

5T/8 11.09 V 1111

3T/4 8.48 V 1011

7T/8 4.59 V 0110

T 0 V 0000

A/D conversion truncates a result, the new code value

will be 1010. The new hex digit is A.

12.31 1⁄2 LSB

12.33 a. Integrating phase: The slope for a Full Scale input is

given by:

_(vin)/RC __16 V/(80 k_)(0.1 _F) __2 V/ms.

Since the slope is proportional to the input voltage, the

slope for a 3 V input is:

(3/16) (_2 V/ms) __0.375 V/ms

take 8 seconds to rezero from Full Scale. This is always

the slope when the circuit rezeros.

c. It would take (3/16) (8 s) _ 1.5 s to rezero for an

input of 3 V.

of 1/4 Full Scale shown in Figure 12.28 in the text.

Q7 10000000 8 V No 0 00000000

Q6 01000000 4 V Yes 1 01000000

Q5 01100000 6 V No 0 01000000

Q4 01010000 5 V No 0 01000000

Q3 01001000 4.5 V Yes 1 01001000

Q2 01001100 4.75 V Yes 1 01001100

Q1 01001110 4.875 V No 0 01001100

Q0 01001101 4.8125 V No 0 01001100

sampled analog waveform. This is 1-1/12 periods, or 30

degrees greater than the sampled waveform. Thus one full

cycle of the alias frequency is 5.2 _s 12 _ 62.4 _s.

The alias frequency is approximately 16 kHz.

12.41 —— adc_cont.vhd

—— State machine interface to ADC0808

—— Continuous conversion, single latch,

—— analog channel selected externally

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY adc_cont IS

PORT(

sc, oe, en : OUT STD_LOGIC);

END adc_cont;

ARCHITECTURE adc OF adc_cont IS

Answers to Selected Odd-Numbered Problems 835

TYPE state_type IS (start, wait1, wait2, read, store);

SIGNAL state: state_type;

SIGNAL outputs: STD_LOGIC_VECTOR (1 to 3);

BEGIN

PROCESS (clock, reset)

IF (reset = ‘0’) THEN

state <= start;

outputs <= “000”;

ELSIF (clock‘EVENT and clock = ‘1’) THEN

CASE state IS

WHEN start =>

state <= wait1;

outputs <= “100”;

WHEN wait1 =>

IF (eoc = ‘1’) THEN

state <= wait1;

outputs <= “000”;

ELSIF (eoc = ‘0’) THEN

state <= wait2;

outputs <= “000”;

END IF;

WHEN wait2 =>

state <= wait2;

outputs <= “000”;

ELSIF (eoc = ‘1’) THEN

state <= read;

outputs <= “011”;

END IF;

WHEN read =>

outputs <= “010”;

WHEN store =>

state <= start;

outputs <= “000”;

END CASE;

END IF;

sc <= outputs(1);

en <= outputs(3);

END PROCESS;

END adc;

Thus, an 8 8 memory requires 3 address lines

(23 _ 8). A 16 8 memory requires 4 address lines

(24 _ 16).

lines

lines

lines

the flow of data into or out of the RAM shown by enabling

or disabling the two tristate buffers on each pin.

There is an output (read) buffer and an input (write)

buffer for each pin.

The read buffers are enabled when W_ _ 1, E_ _ 0,

and G_ _ 0. The write buffers are enabled when W_ _ 0

and E_ _ 0. G_ is not required for the write buffer. Thus W_

controls the direction of the data (read or write), E_ enables

the tristate buffers in either direction, and G_ enables

the output buffers only.

13.7 To change the cell contents to a 0, we make the BIT line

LOW and the ROW SELECT line HIGH. The ROW SELECT

line gives access to the cell by turning on Q5 and

Q6, completing the conduction path between the BIT

lines and the flip flop inputs. The LOW on the BIT line

pulls the gate of Q4 LOW, turning it OFF. This breaks the

conduction path from Q4 drain to source and makes VDS4

_VDD, a logic HIGH. This HIGH is applied to the gate

of Q3, turning it ON. A conduction path is established between

Q3 drain and source, pulling the drain of Q3 LOW.

The cell now stores a logic 0.

13.9 A selected RAM cell is at the junction of an active ROW

line and an active COLUMN line in a rectangular matrix

of cells.

13.11 The DRAM in Problem 13.10 has 10 multiplexed

ROW/COLUMN address lines. Adding one more line

makes 11 lines, each of which are used for a ROW address

and also a column address. This make a total of 22

lines, giving an address capacity of 222 _ 4M locations.

Adding another address line gives 12 multiplexed lines,

each used for ROW and COLUMN, giving a total of

224 _ 16M locations.

of ROM is how easy each type is to program and

erase.

Mask-programmed ROM has the data manufactured

into the device, making it difficult to program and

impossible to erase. It is relatively cheap to mass-produce

and is useful for storing unchanging data that must always

be retained, including after power failure. An example

is the “boot ROM” in a personal computer that contains

data for minimal start-up instructions.

UV-erasable EPROM is fairly expensive because of

the specialized packaging it requires. It is user-programmable

and can be easily erased by exposure to ultraviolet

light when removed from the circuit. It is useful for unfinished

designs, since stored data can be changed as development

of a product proceeds.

data to be stored after power is removed from a device,

but which require periodic in-circuit changes of

data. One example might be an EEPROM which stores

the numbers of several local channels in a digitally-programmed

car radio.

that can be erased all at one time. One sector, called the

boot block, can be protected against unauthorized erasure

or modification, thus adding a level of security to the

memory.

13.17 EEPROM has slower access time and smaller bit capacity

than RAM. It also has a finite number of program/erase

cycles.

13.19 FIFO: buffer for serial data transmission; LIFO: memory

stack in a microcomputer

(000H to FFFH); End address _ Start _ Maximum _

2000H _ FFFH _ 2FFFH.

8K _ 213. Range _ 0 0000 0000 0000 to 1 1111 1111

1111 (0000H to 1FFFH);

End _ Start _ Maximum _ 6000H _ 1FFFH _ 7FFFH

See Figure ANS13.21.

13.23 See Figure ANS13.23

4 K

2000H

7FFFH

FFFFH

Answers to Selected Odd-Numbered Problems 837

EPROM 0000H 3FFFH 16K

SRAM1 4000H 7FFFH 16K

SRAM2 8000H BFFFH 16K

SRAM3 E000H FFFFH 8K

Device Start Address End Address

0 0000000H 0FFFFFFH

1 1000000H 1FFFFFFH

2 2000000H 2FFFFFFH

3 3000000H 3FFFFFFH

4 4000000H 4FFFFFFH

5 5000000H 5FFFFFFH

6 6000000H 6FFFFFFH

7 7000000H 7FFFFFFH

8 8000000H 8FFFFFFH

9 9000000H 9FFFFFFH

10 A000000H AFFFFFFH

11 B000000H BFFFFFFH

12 C000000H CFFFFFFH

13 D000000H DFFFFFFH

14 E000000H EFFFFFFH

15 F000000H FFFFFFFH

RAM0

0000H

8000H

A000H

RAM2