Chapter 1 Basic Principles of Digital Systems outlin e 1
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a. Half Adder Circuit b. Symbol SUM
CARRY A B 1 FIGURE ANS4.9 FIGURE ANS4.11 B INPUT VCC A INPUT VCC halfadd
CARRY_IN INPUT
VCC A SUM CARRY A B 11 halfadd
SUM CARRY
A OR2
10 B 12 SUM OUTPUT
B CARRY_OUT OUTPUT
—— 4-to-1 multiplexer —— Directs one of four input signals (d0 to d3) to output, —— depending on status of select bits (s1, s0). —— STD_LOGIC types LIBRARY ieee; USE ieee.std_logic_1164.ALL; —— Define inputs and outputs ENTITY mux4 IS PORT( d0, d1, d2, d3 : IN STD_LOGIC; —— data inputs s: IN STD_LOGIC_VECTOR (1 downto 0); — — select inputs y: OUT STD_LOGIC); END mux4; —— Define i/o relationship ARCHITECTURE mux4to1 OF mux4 IS BEGIN
— — Choose a signal assignment for y — — based on binary value of d — — Default case: output LOW WITH s SELECT y <= d0 WHEN “00”, d1 WHEN “01”, d2 WHEN “10”, d3 WHEN “11”, ‘0’ WHEN others; END mux4to1; 4.23 —— dmux4.vhd —— 4-channel demultiplexer —— Directs input to one of four outputs, —— depending on state of select inputs (s1, s0) —— Standard VHDL models LIBRARY ieee; USE ieee.std_logic_1164.ALL; —— Define inputs and outputs ENTITY dmux4 IS PORT(
d, s1, s0 : IN STD_LOGIC; y0, y1, y2, y3 : OUT STD_LOGIC); END dmux4; —— Define i/o relationship ARCHITECTURE four_ch_dmux OF dmux4 IS BEGIN
— — Concurrent Signal Assignment y0 <= (not s1) and (not s0) and d; y1 <= (not s1) and ( s0) and d; y2 <= ( s1) and (not s0) and d; y3 <= ( s1) and ( s0) and d; END four_ch_dmux; 4.25 —— half add.vhd —— Half Adder —— Adds two bits, A and B and produces SUM and CARRY outputs —— Standard VHDL models Answers to Selected Odd-Numbered Problems 785 LIBRARY ieee; USE ieee.std_logic_1164.ALL; —— Define inputs and outputs ENTITY half_add IS PORT(
a, b : IN STD_LOGIC; sum, carry : OUT STD_LOGIC); END half_add; —— Define relationship between A, B and SUM, CARRY ARCHITECTURE half_adder OF half_add IS BEGIN
— — Concurrent Signal Assignment sum <= a xor b; carry <= a and b; END half_adder; AND3 NOT
NOT NOT AND3
AND3 AND3
Y0 OUTPUT
Y1 OUTPUT
Y2 OUTPUT
Y3 OUTPUT
D1 INPUT
D0 INPUT
G INPUT
4.27 The gdf for the full adder with VHDL half adder components is the same as Figure ANS4.13. Chapter 5 5.1 1100, 0001, 1111; Y _ D3D2D_1D_0; Y _ D_3D_2D_1D0; Y _ D3D2D1D0 5.3 See Figure ANS5.3. FIGURE ANS5.3 786 Answers to Selected Odd-Numbered Problems 5.5 a 32; b. 64; c. 256; m _ 2n. 5.7 A selected signal assignment assigns an output value based on alternative input values. Each choice is independent of the others. A conditional signal assignment evaluates one input choice and assigns a value to an output if true. Otherwise, a second choice is evaluated, then a third, and so on. Low-priority choices are assigned only if higher-priority alternatives are false. This linked conditional structure tends to generate a more “serial” hardware, as opposed to the more “parallel” structure of the selected signal assignment. The selected signal assignment is preferable because it is generally results in a better use of chip resources and is more efficient. 5.9 See Figures ANS5.9a and ANS5.9c. FIGURE ANS5.9C FIGURE ANS5.9A Answers to Selected Odd-Numbered Problems 787 5.11 See Figure ANS5.11. 5.13 a _ D_3D_2D_1D0 _ D_3D2D_1D_0 _ D3D_2D1D0 _ D3D2D_1D0 b _ D_3D2D_1D0 _ D3D2D1 _ D3D2D_0 _ D3D1D0 _ D2D1D_0
c _ D_3D_2D1D_0 _ D3D2D_1D_0 _ D3D2D1 d _ D_3D_2D_1D0 _ D_3D2D_1D_0 _ D3D_2D1D_0 _ D2D1D0 e _ D_3D0 _ D_3D2D_1 _ D_2D_1D0 f _ D_3D_2D0 _ D_3D_2D1 _ D_3D1D0 _ D3D2D_1D0 g _ D_3D_2D_1 _ D_3D2D1D0 _ D3D2D_1D_0
0 0 0 D0
0 0 1 D1 0 1 0 D2
0 1 1 D3 1 0 0 D4
1 0 1 D5 1 1 0 D6
1 1 1 D7 Truth Table for a 16-to-1 MUX S3 S2 S1 S0 Y 0 0 0 0 D0 0 0 0 1 D1 0 0 1 0 D2 0 0 1 1 D3 0 1 0 0 D4 0 1 0 1 D5 0 1 1 0 D6 0 1 1 1 D7 1 0 0 0 D8 1 0 0 1 D9 1 0 1 0 D10 1 0 1 1 D11 1 1 0 0 D12 1 1 0 1 D13 1 1 1 0 D14 1 1 1 1 D15
D8 INPUT D9 INPUT
D7 INPUT
D6 INPUT
D5 INPUT
D3 INPUT
D4 INPUT
NOT AND3
AND3 AND3
AND3 OUTPUT Q2 OUTPUT Q3 OUTPUT Q1 OUTPUT Q0 AND6
AND6 AND3
AND3 AND3
D2 INPUT
D1 INPUT
NOT NOT
NOT NOT
NOT NOT
NOT NOT
AND4 AND6
AND2 AND3
VCC OR4
OR4 OR6
GND FIGURE ANS5.19A Answers to Selected Odd-Numbered Problems 789 FIGURE ANS5.19B FIGURE ANS5.21 790 Answers to Selected Odd-Numbered Problems 5.27 —— quad8to1.vhd —— Eight-channel 4-bit multiplexer —— One of eight sets four inputs —— (d03..d00), (d13..d10), (d23..d20), (d33..d30), —— (d43..d40), (d53..d50), (d63..d60), (d73..d70) —— is directed to an output (y), based on the status of three —— select inputs (s2, s1, s0). ENTITY quad8to1 IS PORT( s : IN INTEGER RANGE 0 to 7; d0 : IN BIT_VECTOR (3 downto 0); d1 : IN BIT_VECTOR (3 downto 0); d2 : IN BIT_VECTOR (3 downto 0); d3 : IN BIT_VECTOR (3 downto 0); d4 : IN BIT_VECTOR (3 downto 0); d5 : IN BIT_VECTOR (3 downto 0); d6 : IN BIT_VECTOR (3 downto 0); d7 : IN BIT_VECTOR (3 downto 0); y : OUT BIT_VECTOR (3 downto 0)); END quad8to1; D0 D1
D3 D4 D5 D6 D7
b. 16-to-1 S2 S1 S0
Y D0 D1 D2 D3 D4 D5 D6 D7 Y D8 D9 D10 D11 D12
D13 D14
D15 S3 S2 S1 S0 FIGURE ANS5.23 5.23 See Figure ANS5.23 See page 787 for Truth Tables. 5.25 Y _ S_2S_1S_0D0 _ S_2S_1S0D1 _ S_2S1S_0D2 _ S_2S1S0D3 _ S2S_1S_0D4 _ S2S_1S0D5 _ S2S1S_0D6 _ S2S1S0D7 _ 1_ _ 0_ _ 1_ _ D0 _ 1_ _ 0_ _ 1 _ D1 _ 1_ _ 0 _ 1_ _ D2 _ 1_ _ 0 _ 1 _ D3 _ 1 _ 0_ _ 1_ _ D4 _ 1 _ 0_ _ 1 _ D5 _ 1 _ 0 _ 1_ _ D6 _ 1 _ 0 _ 1 _ D7 _ 0 _ D0 _ 0 _ D1 _ 0 _ D2 _ 0 _ D3 _ _D4 _ 1 _ D5 _ 0 _ D6 _ 0 _ D7 _ D5
Answers to Selected Odd-Numbered Problems 791 ARCHITECTURE mux8 OF quad8to1 IS BEGIN —— Selected Signal Assignment MUX4: WITH s SELECT y <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3, d4 WHEN 4, d5 WHEN 5, d6 WHEN 6, d7 WHEN 7; END mux8; FIGURE ANS5.27 The simulation of this circuit is shown in Figure ANS5.27. 5.29 —— oct4to1.vhd —— Four-channel 8-bit multiplexer —— One of four sets eight inputs —— (d07..d00), (d17..d10), (d27..d20), or (d37..d30) —— is directed to a an output (y), based on the status of two —— select inputs (s1, s0). ENTITY oct4to1 IS PORT(
s : IN INTEGER RANGE 0 to 3; d0 : IN BIT_VECTOR (7 downto 0); d1 : IN BIT_VECTOR (7 downto 0); d2 : IN BIT_VECTOR (7 downto 0); d3 : IN BIT_VECTOR (7 downto 0); y : OUT BIT_VECTOR (7 downto 0)); 792 Answers to Selected Odd-Numbered Problems END oct4to1; ARCHITECTURE mux4 OF oct4to1 IS BEGIN
—— Selected Signal Assignment MUX8: WITH s SELECT y <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3; END mux4; The simulation is shown in Figure ANS5.29. 5.31 ENTITY mux_8ch IS PORT(
sel : IN BIT_VECTOR (2 downto 0); d : IN BIT_VECTOR (7 downto 0); y : OUT BIT); END mux_8ch; ARCHITECTURE a OF mux_8ch IS BEGIN
—— Selected Signal Assignment MUX8: WITH sel SELECT y <= d(0) WHEN “000”, d(1) WHEN “001”, d(2) WHEN “010”, d(3) WHEN “011”, d(4) WHEN “100”, d(5) WHEN “101”, d(6) WHEN “110”,
d(7) WHEN “111”; END a;
An 8-to-1 MUX can be easily extended to a 16-bit device by adding one select input, eight data inputs, and eight Answers to Selected Odd-Numbered Problems 793 NOT
NOT S2 INPUT S1 INPUT
S0 INPUT
DATA INPUT
NOT AND4
Y0 OUTPUT
AND4 Y6 OUTPUT AND4 Y5 OUTPUT AND4 Y4 OUTPUT AND4 Y3 OUTPUT AND4 Y2 OUTPUT AND4 Y1 OUTPUT AND4 Y7 OUTPUT FIGURE ANS5.37A 794 Answers to Selected Odd-Numbered Problems X0 X1 X2 X3 Y0 Y1 Y2 Y3 74HC4052 X CTR DIV 4 Y S1 S0
Q1 CLOCK
Q0 Telephone System Transmit
channels Receive
channels FIGURE ANS5.37B FIGURE ANS5.41 5.39 An analog switch can transmit a range of positive and negative voltages, not just 0V and 5V. 5.41 See Figure ANS5.41 5.43 See Figure ANS5.43. The glitch in the simulation is caused by propagation delay. 5.45 AEQB _ (A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _)(A_2 ____B_2 _) (A_1 ____B_1 _)(A_0 ____B_0 _) AGTB _A5B_5 _A4B_4(A_5 ____B_5 _) _ A3B_3(A_5 ____B_5 _)(A_4 ____B_4 _) _A2B_2(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) _A1B_1(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) (A_2 ____B_2 _) _A0B_0(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) (A_2 ____B_2 _)(A_1 ____B_1 _) ALTB _A_5B5 _A_4B4(A_5 ____B_5 _) _A_3B3 (A_5 ____B_5 _)(A_4 ____B_4 _) _A_2B2(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) _A_1B1(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) lines to the selected signal assignment statement. 5.35 00110011; 00001111 5.37 See Figure ANS5.37. Answers to Selected Odd-Numbered Problems 795 (A_2 ____B_2 _) _A_0B0(A_5 ____B_5 _)(A_4 ____B_4 _)(A_3 ____B_3 _) (A_2 ____B_2 _)(A_1 ____B_1 _)
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY cmp4x6 IS PORT( NOT
NOT NOT
A3 INPUT
B3 INPUT
A2 INPUT
B2 INPUT
B1 INPUT
A1 INPUT
NOT AND4
AND6 OR4
VCC AND3
AND2 XNOR
XNOR XNOR
OUTPUT A_LT_B A0 INPUT B0 INPUT
FIGURE ANS5.43 796 Answers to Selected Odd-Numbered Problems a, b : IN INTEGER RANGE 0 TO 15; altb, aleb, aeqb, aneb, ageb, agtb : OUT STD_LOGIC); END cmp4x6; ARCHITECTURE a OF cmp4x6 IS SIGNAL compare : STD_LOGIC_VECTOR (5 downto 0); BEGIN PROCESS (a,b) BEGIN IF a compare <= “001011”; ELSIF a=b THEN compare <= “100101”; ELSIF a>b THEN compare <= “111000”; ELSE
compare <= “111111”; END IF;
altb <= compare (5); — — a is less than b aleb <= compare (4); — — a is less than or equal to b aeqb <= compare (3); — — a equals b aneb <= compare (2); — — a is not equal to b A INPUT
B INPUT
C INPUT
D INPUT
OUTPUT XOR
XOR XOR
XOR XOR
XOR nEVEN_ODD INPUT E
P_send INPUT
P_check FIGURE ANS5.53 ageb <= compare (1); — — a is greater than or equal to b agtb <= compare (0); — — a is greater than b END PROCESS; END a;
parity bit. c. ABCDEFGHP _ 110001100; P_ _ 0; Data received Answers to Selected Odd-Numbered Problems 797 correctly.
E and F
undetected 5.53 See Figure ANS5.53. Chapter 6 6.1 a. 11111; b. 100000; c. 11110; d. 101010; e. 101100; f. 1100100 6.3 True 1’s 2’s Decimal Magnitude Complement Complement a. _110 11101110 10010001 10010010 b. 67 01000011 01000011 01000011 c. _54 10110110 11001001 11001010 d. _93 11011101 10100010 10100011 e. 0 00000000 00000000 00000000 f. _1 10000001 11111110 11111111 g. 127 01111111 01111111 01111111 h. _127 11111111 10000000 10000001 6.5 Largest: 011111112__12710; smallest: 100000002__12810 6.7 Overflow in an 8-bit signed addition results if the sum is outside the range _128 _ sum _ _ 127. The sums in parts a. and f. do not generate an overflow. The sums in parts b., c., d., and e. do. c. B1A; d. FFF; e. 2A7F 6.11 6.15 The sequence of codes yields the following text: 6.21 A fast carry circuit is “flatter”, but “wider” than a ripple carry circuit. There are more gate levels for an input change to propagate through in a ripple carry circuit. The ripple carry is thus slower. The limitation on a fast carry circuit is its width, both in the number of gates and on the number of inputs on the gates. Both factors increase with adder bit size.
AND the second bit of either A or B is HIGH AND the third bits of both A and B are HIGH.
8-bit adder requires 216_65,536 combinations. (A simulation with one change every 40 ns would have an end time of 2.62144 ms.) 6.27 See Figure ANS6.27 The transition from the sum FFF_000_FFF to FFF_001_000 (plus a carry) is given in the following table:
Time Sum (Hex) Sum (Binary) From a1 to: 0 FFF 1111 1111 1111 8421 BCD Excess-3 0111 0000 1001 1010 0011 1100 0001 1000 1000 1001 0100 1011 1011 1100 0010 0011 1001 0101 0101 0110 1100 1000 0001 0010 0101 1001 0100 0101 1000 1100 0011 1001 0111 0010 0110 1100 1010 0101 0111 0111 0011 0000 1010 1010 0110 0011
709 1011000101 1889 11101100001 2395 100101011011 1259 10011101011 3972 111110000100 7730 1111000110010 57 41 52 4E 49 4E 47 21 20 54 68 69 73 20 W A R N I N G ! SP T h i s SP 63 6F 6D 6D 61 6E 64 20 65 72 61 73 65 73 c o m m a n d SP e r a s e s 20 36 34 30 4D 20 6F 66 20 6D 65 6D 6F 72 79 2E SP 6 4 0 M SP o f SP m e m o r y .
7.5 ns FFC 1111 1111 1100 sum1, sum2 12.5 ns FC0 1111 1100 0000 sum3-sum6 17.5 ns F00 1111 0000 0000 sum7, sum8 22.5 ns E00 1110 0000 0000 sum9 26.5 ns C00 1100 0000 0000 sum10 FULL_ADD sum1
OUTPUT c1 OUTPUT a b c_in sum a1 c_out
INPUT b1 INPUT c0 INPUT
FULL_ADD sum2
OUTPUT c2 OUTPUT a b c_in sum a2 c_out
INPUT b2 INPUT FULL_ADD sum3
OUTPUT c3 OUTPUT a b c_in sum a3 c_out
INPUT b3 INPUT FULL_ADD sum4
OUTPUT c4 OUTPUT a b c_in sum a4 c_out
INPUT b4 INPUT FIGURE ANS6.29B FIGURE ANS6.29A A1 INPUT A2 INPUT
A3 INPUT
A4 INPUT
SUB INPUT
B1 INPUT
B2 INPUT
B3 INPUT
B4 INPUT
a1 b1 c1 a2 b2 a3 b3 a4 b4 c1 sum1
c2 sum2
c3 sum3
c4 sum4
add4 OUTPUT
OUTPUT OUTPUT
SUM1 SUM2
SUM3 C4 OUTPUT SUM4 OUTPUT
XOR XOR
XOR XOR
31.5 ns 000 0000 0000 0000 sum11, sum12 6.29 The 4-bit parallel adder/subtractor is shown in Figure ANS6.29a. The component add4, a parallel binary adder, is shown in Figure ANS6.29b. SUB _ 1: Input carry is forced HIGH, automatically Answers to Selected Odd-Numbered Problems 799 A1 INPUT A2 INPUT
A3 INPUT
A4 INPUT
SUB INPUT
B1 INPUT
B2 INPUT
B3 INPUT
B4 INPUT
A1 A2 A3 A4 SUB
B1 B2 B3 B4 SUM1
OUTPUT addsub4
overflow SUM2
OUTPUT SUM3
OUTPUT C4 OUTPUT SUM4 S1 S2 S4 C4 S4 OUTPUT V OUTPUT SA SB S_SUM V SA INPUT SB INPUT
NOT NOT
S_SUM INPUT
OUTPUT AND3
AND3 OR2
V NOT
FIGURE ANS6.31 adding 1 to the output sum; the XOR gates act as inverters, making the inputs to the adder equal to the one’s complement of B; the output is A _ (one’s complement of B) _ 1 _A _ B SUB _ 0: Input carry is forced LOW, adding 0 to the output sum; the XOR gates act as noninverting buffers, making the inputs to the adder equal the true binary value of B; the output is A _ B _ 0 _A _ B.
—— 4-bit parallel adder with overflow detection, —— using a generate statement and components —— overflow: SOP network ENTITY addsubv1 IS PORT(
sub : IN BIT; a, b : IN BIT_VECTOR(4 downto 1); c4, v : OUT BIT; sum : BUFFER BIT_VECTOR(4 downto 1)); END addsubv1; ARCHITECTURE adder OF addsubv1 IS —— Component declaration COMPONENT full_add PORT( a, b, c_in : IN BIT; c_out, sum : OUT BIT); 800 Answers to Selected Odd-Numbered Problems END COMPONENT; —— Define a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0); SIGNAL b_comp : BIT_VECTOR (4 downto 1); BEGIN
—— Carry input depends on add or subtract (sub=1 for subtract) c(0) <= sub; adders: FOR I IN 1 to 4 GENERATE —— invert b for subtract function (b(i) xor 1) —— do not invert b for add function (b(i) xor 0) b_comp(i) <= b(i) xor sub; adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i), sum(i)); END GENERATE; c4 <= c(4); v <= (a(4) and b(4) and (not sum(4))) or ((not a(4)) and (not b(4)) and sum(4)); END adder; —— addsubv2.vhd —— 4-bit parallel adder with overflow detection, —— using a generate statement and components —— overflow: xor gate ENTITY addsubv2 IS PORT( sub : IN BIT; a, b : IN BIT_VECTOR(4 downto 1); c4, v : OUT BIT; sum : OUT BIT_VECTOR(4 downto 1)); END addsubv2; ARCHITECTURE adder OF addsubv2 IS —— Component declaration COMPONENT full_add PORT(
a, b, c_in : IN BIT; c_out, sum : OUT BIT); END COMPONENT; —— Define a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0); SIGNAL b_comp : BIT_VECTOR (4 downto 1); BEGIN —— Carry input depends on add or subtract (sub=1 for subtract) c(0) <= sub; adders:
FOR i IN 1 to 4 GENERATE —— invert b for subtract function (b(i) xor 1) —— do not invert b for add function (b(i) xor 0) b_comp(i) <= b(i) xor sub; adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i), sum(i)); END GENERATE; c4 <= c(4); v <= c(4) xor c(3); END adder; Answers to Selected Odd-Numbered Problems 801 Directory: uploads uploads -> 587 Return function, r i(X) r i(0) r i(1) r i(2) r i(3) 1 0 2 4 6 Thermal Station, I 2 0 1 5 6 3 0 3 5 6 10 uploads -> Department of science and humanities department of mathematics part-a questions and answers uploads -> The Case Against the nypd’s Quota-Driven ‘Broken Windows’ Policing What Is It? uploads -> For want of a nail uploads -> Ownership Models There are two different types of ownership models uploads -> Police Militarization uploads -> City of rising star regular meting thursday, july 14, 2016 uploads -> Township of winfield uploads -> Stop Militarizing Law Enforcement Act of 2014 uploads -> The Black Panther Party’s Ten-Point Program What We Want Now! Download 10.44 Mb. Share with your friends:
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