Chapter 1 Basic Principles of Digital Systems outlin e 1
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6.35 1999; 31⁄2 digits 6.37 1 followed by n 9s. 6.39 See Figure 6.26 in text. 6.41 —— add4bcd.vhd —— 4-bit bcd adder LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY add4bcd IS PORT(
c0 : IN STD_LOGIC: a_bcd, b_bcd : IN STD_LOGIC_VECTOR(4 down to 1); sum_bcd : OUT STD_LOGIC_VECTOR(5 downto 1)); END add4bcd; ARCHITECTURE adder OF add4bcd IS —— Component declaration COMPONENT add4gen PORT(
c0 : IN STD_LOGIC; a, b : IN STD_LOGIC_VECTOR(4 downto 1); c4 : OUT STD_LOGIC; sum : OUT STD_LOGIC_VECTOR(4 downto 1)); END COMPONENT; COMPONENT bin2bcd PORT( bin : IN STD_LOGIC_VECTOR(5 downto 1); bcd : OUT STD_LOGIC_VECTOR(5 downto 1); END COMPONENT; —— Define a signal for internal carry bits SIGNAL connect : STD_LOGIC_VECTOR (5 downto 1); BEGIN adder: add4gen PORT MAP (c0, a_bcd, b_bcd, connect(5), connect (4 downto 1)); converter: bin2bcd PORT FIGURE ANS7.1 FIGURE ANS7.3 802 Answers to Selected Odd-Numbered Problems MAP (connect, sum_bcd); S (or S) R (or R)
Q Q
S (or S) R (or R)
Q Q
FIGURE ANS7.9 S Q R Q
S R
Q FIGURE ANS7.7 END adder; 6.43 The circuit will be like Figure 6.27 in the text, minus the thousands digit. It will generate a 31⁄2 digit output. Chapter 7 7.1 See Figure ANS7.1. 7.3 See Figure ANS7.3. 7.5 See Figure ANS7.5. S_ R_ 0 0 Latch tries to set and reset at the same time. Forbidden state. 0 1 Set input active. Q _ 1. 1 0 Reset input active. Q _ 0. 1 1 Neither set nor reset active. No change.
Answers to Selected Odd-Numbered Problems 803 S R
Q i. S R Q Q ii. S R Q Q iii. FIGURE ANS7.11 FIGURE ANS7.13 804 Answers to Selected Odd-Numbered Problems 7.11 a. See Figure ANS7.11. b. i. R is last input active. Latch resets; ii. S is last in FIGURE ANS7.17 FIGURE ANS7.15 Answers to Selected Odd-Numbered Problems 805 FIGURE ANS7.19 EN/CLK
D Q1 Q2 FIGURE ANS7.21 7.19 —— ltch8prm.vhd —— D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY ltch8prm IS PORT(d_in : IN STD_LOGIC_VECTOR(7 downto 0); enable : IN STD_LOGIC; q_out : OUT STD_LOGIC_VECTOR(7 downto 0)); END ltch8prm; ARCHITECTURE a OF ltch8prm IS BEGIN —— Instantiate a latch from a MAX_PLUS II primitive latch8: FOR i IN 7 downto 0 GENERATE latch_primitive: latch PORT MAP (d => d_in(i), ena => enable, q => q_out(i)); END GENERATE; END a;
See Figure ANS7.19. 7.21 See Figure ANS7.21. 806 Answers to Selected Odd-Numbered Problems 7.23 See Figure ANS7.23. 7.25 See Figure ANS7.25. FIGURE ANS7.23 FIGURE ANS7.25 7.27 —— dff12lpm.vhd —— 12-BIT D flip-flop —— Uses a flip-flop component from the Library of Parameterized Modules (LPM) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY dff12lpm IS PORT(d_in : IN STD_LOGIC_VECTOR(11 downto 0); clk : IN STD_LOGIC; q_out : OUT STD_LOGIC_VECTOR(11 downto 0)); END dff12lpm; ARCHITECTURE a OF dff12lpm IS BEGIN
—— Instantiate flip-flop from an LPM component dff12: lpm_ff GENERIC MAP (LPM_WIDTH => 12) PORT MAP (data => d_in, clock => clk, q => q_out); END a; Answers to Selected Odd-Numbered Problems 807 7.29 See Figure ANS7.29. 7.31 See Figure ANS7.31. The circuit generates the following repeating pattern: 111, 110, 101, 100, 011, 010, 001, 000. This is a 3-bit binary down-count sequence. 0 1 2 CLK
J Q Q K PRE
CLR FIGURE ANS7.31 FIGURE 7.35 FIGURE ANS7.29 7.33 The circuit generates a 4-bit binary sequence from 0000 to 1111, then repeats indefinitely. 7.35 See Figure 7.35. 808 Answers to Selected Odd-Numbered Problems 7.37 See Figure 7.37 7.39 Similarity: an asynchronous circuit and an asynchronous input cause outputs to change out of synchronization with a system clock. Difference: an asynchronous circuit may be clocked, but at different times throughout the circuit; an asynchronous input is independent of the clock function altogether. RESET OUTPUT
q3 AND2 AND3 OUTPUT q2
INPUT q1 OUTPUT q0 clock
INPUT JKFF
CLRN PRN
J Q K JKFF CLRN PRN
J Q K JKFF CLRN PRN
J Q K JKFF VCC CLRN
PRN J Q
K FIGURE 7.37 7.41 —— d121pmcl.vhd —— 4-BIT D latch with active-HIGH level-sensitive enable —— Uses a latch component from the Library of Parameterized Modules LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY d12lpmcl IS PORT(d_in : IN STD_LOGIC_VECTOR(11 downto 0); clk, set, reset : IN STD_LOGIC; q_out : OUT STD_LOGIC_VECTOR(11 downto 0)); END d12lpmcl; ARCHITECTURE a OF d12lpmcl IS SIGNAL clrn : STD_LOGIC; SIGNAL prn : STD_LOGIC; Answers to Selected Odd-Numbered Problems 809 BEGIN —— Instantiate flip-flop from an LPM component dff12: lpm_ff GENERIC MAP (LPM_WIDTH => 12) PORT MAP ( data => d_in, clock => clk, aclr => clrn, aset => prn, q => q_out); —— Make set and reset active-LOW clrn <= not reset; prn <= not set; END a; CLK
T Q
FIGURE ANS7.41 7.43 See Figure ANS7.43. 7.45 —— syn4tprm.vhd —— 4-bit sync counter (TFF primitives) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY syn4tprm IS PORT (clock, reset : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(3 downto 0)); END syn4tprm; 810 Answers to Selected Odd-Numbered Problems ARCHITECTURE a OF syn4tprm IS —— Declare component only with ports actually used COMPONENT TFF PORT ( t : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; SIGNAL q_int : STD_LOGIC_VECTOR(2 downto 0); SIGNAL t_int : STD_LOGIC_VECTOR(3 downto 0); BEGIN
—— Instantiate 4 T flip-flops. ff0: tff
PORT MAP (t_int(0), clock, reset, q_int(0)); ff1: tff
PORT MAP (t_int(1), clock, reset, q_int(1)); ff2: tff
PORT MAP (t_int(2), clock, reset, q_int(2)); ff3: tff
PORT MAP (t_int(3), clock, reset, q(3)); —— Connect flip-flops internally t_int(0) <= ‘1’; t_int(1) <= q_int(0); t_int(2) <= q_int(0) and q_int(1); t_int(3) <= q_int(0) and q_int(1) and q_int(2); q(0) <= q_int(0); q(1) <= q_int(1); q(2) <= q_int(2); END a;
7.47 tsu _ 20 ns, th _ 0 7.49 clock pulse width: tw _ 12 ns; setup time: tsu _ 10 ns; hold time: th _ 5 ns Chapter 8 8.1 See Figure 8.2. 8.7 a. 4; b. 6; c. 8 8.9 A global architecture cell configures all macrocells in the PLD. A local architecture cell works only on the macrocell of which it is a part.
active LOW; combinatorial/active HIGH 8.13 No. Global clock only. 8.15 Global. These functions operate simultaneously on all macrocells. 8.17 a. 32; b. 64; c. 128; d. 160 8.19 n/16 LogicArrayBlocks for n macrocells. (e.g. 128/16_8 LABs for an EPM7128S) 8.21 Macrocells without pin connections can be used for internal logic.
8.23 A MAX7000S macrocell can be reset from a global clear pin (GCLRn) or locally from a product term. 8.25 5 dedicated product terms; by using terms from shared logic expanders and parallel logic expanders; 5 dedicated, up to 15 from parallel logic expanders; up to 16 from shared logic expanders. 8.27 A sum-of-products network constructs Boolean expressions by switching signals into an OR-gate output via a programmable matrix of AND gates. A look-up table network stores the output values of the network in a small memory whose storage locations are selected by combinations of the input signals. 8.29 A carry chain allows for efficient fast-carry implementation of adders, comparators, and other circuits whose inputs become wider with higher-order bits.
Answers to Selected Odd-Numbered Problems 811 Chapter 9 9.1 See Figure ANS9.1. The 12-bit counter recycles to 0 after 4096 cars have entered the parking lot. The last car causes all bits to go LOW. The negative edge on the MSB clocks a flip flop whose output enables the LOT FULL sign. Every car out of the gate resets the flip-flop and turns off the sign. A better circuit would have the exit gate make the counter output decrease by 1 with every vehicle exiting. 9.3 See Figure ANS9.3. CLK
Q0 Q1 Q2 Recycle 0000
0001 0010
0011 0100
0101 0110
0111 1000
1001 FIGURE ANS9.1 FIGURE ANS9.3 FIGURE ANS9.5 9.5 a. See Figure ANS9.5 b. i. 0100; ii. 0110; iii. 0011 812 Answers to Selected Odd-Numbered Problems 9.7 Figure ANS9.7 shows the timing diagram of a mod-10 counter.
9.13 J0 _ K0 _ 1 J1 _ K1 _ Q0 J2 _ K2 _ Q1Q0 J3 _ K3 _ Q2Q1Q0 J4 _ K4 _ Q3Q2Q1Q0 J5 _ K5 _ Q4Q3Q2Q1Q0 J6 _ K6 _ Q5Q4Q3Q2Q1Q0 J7 _ K7 _ Q6Q5Q4Q3Q2Q1Q0 9.15 a. J3 _ Q2Q1Q0 K3 _ Q1Q0 J2 _ Q_3Q1Q0 K2 _ Q1Q0 J1 _ Q0 K1 _ Q0
J0 _ 1 K0 _ 1
b. 1011, 0000, 0001 9.19 See Figure ANS9.19 Q3 Q2 Q1 Q0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 1 0 1 0 0
0 1 0 1 0 1 1 0
0 1 1 1 1 0 0 0
1 0 0 1 CLK
Q0 Q1 Q2 Q3 Recycle
FIGURE ANS9.7 FIGURE ANS9.11 OUTPUT
q3 AND2 AND3 OUTPUT q2
q1 OUTPUT
q0 clock
INPUT JKFF
CLRN PRN
J Q K JKFF CLRN PRN
J Q K JKFF CLRN PRN
J Q K JKFF VCC CLRN
PRN J Q
K 9.9 Q0: 24 kHz; Q1: 12 kHz; Q2: 6 kHz; Q3: 3 kHz 9.11 See Figure ANS9.11 AND2
AND3 OR2
OR3 AND2
AND2 AND3
AND2 AND3
OR2 DFF
NOT CLRN
PRN D Q
DFF NOT
CLRN PRN
D Q DFF
NOT CLRN
PRN D Q
DFF NOT
CLRN PRN
D Q CLOCK
INPUT OUTPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 FIGURE ANS9.19 0000
0001 0010
0011 0100 1100 1011 1010 0101
0110 0111
1000 1110
1111 1001
1101 814 Answers to Selected Odd-Numbered Problems FIGURE ANS9.23B 9.21 Boolean equations: D3 _ Q_3Q2 _ Q3Q_2 D2 _ Q1Q0 D1 _ Q_1Q0 _ Q1Q_0 D0 _ Q_2Q_0
and Figure ANS9.23b for the recycle point of the counter.
data directly to the flip-flops of a counter as soon as the load input is asserted; it does not wait for a clock edge. Synchronous load waits for an active clock edge to load a value into the counter flip-flops.
the value 1AH is synchronously loaded into the counter. 9.29 See Figure ANS9.29 9.31 D0 _ Q_0 D1 _ Q0DIR _ Q_0D_I_R_ D2 _ Q1Q0DIR _ Q_1Q_0D_I_R_ D3 _ Q2Q1Q0DIR _ Q_2Q_1Q_0D_I_R_ The right-hand product term of each equation represents the down-count logic, which is enabled whenever DIR _ 0. The left-hand product term is the up-count logic, enabled when DIR _ 1. D0 is always the opposite of Q0, regardless of whether the count is up or down.
Answers to Selected Odd-Numbered Problems 815 FIGURE ANS 9.29 FIGURE ANS9.27 816 Answers to Selected Odd-Numbered Problems RESET
INPUT DIR
INPUT CLOCK
INPUT LOAD
INPUT P[3..0]
INPUT P[3..0] VCC
COUNT sl_count
LOAD P Q
CLOCK RESET
COUNT sl_count
LOAD P Q
CLOCK RESET
COUNT sl_count
LOAD P Q
CLOCK RESET
COUNT sl_count
LOAD P Q
CLOCK RESET
P0 P1 P2 P3 OUTPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 AND4
OR2 AND2
OR2 AND2
OR2 AND2
AND2 BAND4
AND3 BAND3
AND2 BAND2
COUNT_ENA INPUT
FIGURE ANS9.33A 9.33 The circuit is shown in Figure ANS9.33a. The counter module sl_count is shown is Figure 9.25 in the text. The simulation is shown in Figure ANS9.33b. Answers to Selected Odd-Numbered Problems 817 FIGURE ANS9.33B 9.35 —— ct_mod24 —— Presettable counter with synchronous clear and load —— and a modulus of 24 ENTITY ct_mod24 IS PORT( clk : IN BIT; clear, direction : IN BIT; q : OUT INTEGER RANGE 0 TO 23); END ct_mod24; ARCHITECTURE a OF ct_mod24 IS BEGIN PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 23; BEGIN
IF (clk‘EVENT AND clk _ ‘1’) THEN IF (clear = ‘0’) THEN —— Synchronous clear cnt := 0; ELSIF (direction = ‘0’) THEN IF cnt = 0 THEN cnt := 23; ELSE cnt := cnt - 1; END IF; ELSIF (direction = ‘1’) THEN IF cnt = 23 THEN cnt := 0; ELSE cnt := cnt + 1; END IF; END IF;
END IF; q <= cnt; END PROCESS; END a;
See Figure ANS9.35 for simulation. 818 Answers to Selected Odd-Numbered Problems 9.37 —— sst1_lpm.vhd —— 12-bit LPM counter with sst1 and aclr (Chapter problem) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY sst1_lpm IS PORT(
clk : IN STD_LOGIC; clear, set : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (11 downto 0)); END sst1_lpm; ARCHITECTURE a OF sst1_lpm IS BEGIN
counter1: lpm_counter GENERIC MAP (LPM_WIDTH => 12) PORT MAP ( clock => clk, sset => set, aclr => clear, q => q);
END a; FIGURE ANS9.37 FIGURE ANS9.35 The counter in this problem sets to all 1s (1111 1111 1111 _ FFFH), rather than 0111 1111 1111 (_ 7FFH). See Figure ANS9.37 for the simulation of the counter in problem 9.37. Answers to Selected Odd-Numbered Problems 819 9.39 —— lpm8term —— 8-bit presettable counter with synchronous clear and load, —— count enable, a directional control port, —— and terminal count decoding LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY lpm8term IS PORT(
clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR(7 downto 0); max_min : OUT STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 downto 0)); END lpm8term; ARCHITECTURE a OF lpm8term IS SIGNAL cnt : STD_LOGIC_VECTOR(7 downto 0); BEGIN counter1: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP ( clock => clk, updown => direction, cnt_en => count_ena, data => p, sload => load, sclr => clear, q => cnt); q <= cnt; PROCESS (clk, cnt) BEGIN —— Terminal count decoder IF (cnt = “00000000” and direction = ‘0’) THEN max_min <= ‘1’; ELSIF (cnt = “11111111” and direction = ‘1’) THEN max_min <= ‘1’; ELSE max_min <= ‘0’; END IF; END PROCESS; END a;
serial input, only delayed by eight clock pulses and synchronized to the positive edge of the clock.
CLK
SERIAL IN SERIAL OUT FIGURE ANS9.45 J Q Q K SET CLR J Q Q K SET CLR J Q Q K SET CLR J Q Q K SET CLR Data In
Clock Q3 Q2 Q1 Q0
FIGURE ANS9.47 821 822 Answers to Selected Odd-Numbered Problems 9.51 —— Left-shift register of generic width LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY slt_bhv IS GENERIC (width : POSITIVE); PORT(
serial_in, clk : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0)); END slt_bhv; ARCHITECTURE left_shift of slt_bhv IS BEGIN PROCESS (clk) BEGIN IF (clk‘EVENT and clk _ ‘1’) THEN q(width-1 downto 0) <= q(width-2 downto 0) & serial_in; END IF;
END PROCESS; END left_shift; —— 32-bit left-shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY slt32_bhv IS PORT( data_in, clock : IN STD_LOGIC; qo : BUFFER STD_LOGIC_VECTOR(31 downto 0)); END slt32_bhv; ARCHITECTURE left_shift of slt32_bhv IS COMPONENT slt_bhv GENERIC (width : POSITIVE); PORT(
serial_in, clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(31 downto 0)); END COMPONENT; BEGIN
Shift_left_32: slt_bhv GENERIC MAP (width=> 32) PORT MAP (serial_in => data_in, clk => clock, q => qo); END left_shift; Figure ANS9.51 shows a partial simulation of the shift register. Answers to Selected Odd-Numbered Problems 823
instantiated component has an assigned width of 16 bits. The generic map in the instantiated component overrides the default parameter. FIGURE ANS9.51 9.55 —— srg10lpm.vhd —— 10-bit serial shift register (shift right) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY srg10lpm IS PORT(
clk : IN STD_LOGIC; serial_in : IN STD_LOGIC; sync_set : IN STD_LOGIC; serial_out : OUT STD_LOGIC); END srg101pm; ARCHITECTURE lpm-shift of srg10lpm IS COMPONENT lpm_shiftreg GENERIC(LPM_WIDTH: POSITIVE; LPM_SVALUE: STRING); PORT( clock, shiftin : IN STD_LOGIC; sset : IN STD_LOGIC; shiftout : OUT STD_LOGIC); END COMPONENT; BEGIN
Shift_10: lpm_shifreg GENERIC MAP (LPM_WIDTH=> 10, LPM_SVALUE => “960”) PORT MAP (clk, serial_in, sync_set, serial_out); END lpm_shift; Directory: uploads uploads -> 587 Return function, r i(X) r i(0) r i(1) r i(2) r i(3) 1 0 2 4 6 Thermal Station, I 2 0 1 5 6 3 0 3 5 6 10 uploads -> Department of science and humanities department of mathematics part-a questions and answers uploads -> The Case Against the nypd’s Quota-Driven ‘Broken Windows’ Policing What Is It? uploads -> For want of a nail uploads -> Ownership Models There are two different types of ownership models uploads -> Police Militarization uploads -> City of rising star regular meting thursday, july 14, 2016 uploads -> Township of winfield uploads -> Stop Militarizing Law Enforcement Act of 2014 uploads -> The Black Panther Party’s Ten-Point Program What We Want Now! Download 10.44 Mb. Share with your friends:
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