Creating a Physical Design Assignment and Configuration File (acf)

information about the configuration options for a project, including assigned device

and pin numbers.

K E Y T E R M S

The previous sections have concentrated on the design aspects of a project. Of course, the

ultimate goal of this procedure is to create a physical version of the design. Before we can

program our majority vote circuit into hardware, we must assign the input and output pin

numbers on the target CPLD. At that point we can recompile the design file and program

the CPLD.

Assigning Pin Numbers

Before proceeding with this step, make sure that you have assigned a device part number to

the design. Save the file and set the project to the current file.

To assign a pin number, click on the pin to highlight it, then right-click to see the popup

menu in Figure 4.35. Choose Assign, then Pin/Location/Chip. You could also do this

from the Assign menu at the top of the screen.

FIGURE 4.35

Pop-up Menu for Pin Assignments

Pin/Location/Chip Assignment

Dialog Box

Table 4.2 Pin Assignment

for a Majority Vote Circuit

A1 12

C1 18

B2 17

Y 4

Pin Assignments in ACF (Before

Copying)

4.7 • Creating a Physical Design 143

We can assign pin numbers in the dialog box in Figure 4.36.

Type A1 in the Node Name box, 12 in the Pin box and click Add. Type B1 in the

Node Name box, assign this name to pin 16, and click Add. Repeat this procedure until all

names are assigned, as in Table 4.2. When all assignments are complete, click OK.

We can also assign pin numbers by editing the Assignment and Configuration File

(acf), as shown in Figures 4.37 and 4.38. This technique works especially well if you need

to assign pin numbers to a sequence of numerically related inputs and outputs.

Figure 4.37 shows the acf with four pin assignments made. We can add the others easily

by using a copy-and-paste procedure. Highlight the line you wish to copy and copy it to

the Windows clipboard (use Copy in the File menu or the Copy icon on the toolbar or

Ctrl-C). Paste three copies into the acf and modify them so that they represent the remaining

required pin assignments, as shown in Figure 4.38.

Figure 4.39 shows the input pin assignments as they appear in the gdf file.

FIGURE 4.38

Pin Assignments in ACF (After Copying)

Pin Assignments as Seen in gdf File

Programming CPLDs on the Altera UP-1 Circuit Board

Altera CPLDs via the parallel port (LPT port) of an IBM PC or compatible.

(called IEEE Std. 1149.1) for testing and programming devices while they are installed

in a system.

ISP In-system programmability. The ability of a PLD (such as a MAX7000S) to

be programmed without removing it from a circuit board.

configured without removing it from a circuit board.

K E Y T E R M S

FIGURE 4.40

ByteBlaster Parallel Port Download Cable (By Permission of Altera Corporation)

programming data.

from one state to the next.

a continuous chain connection. Such a chain allows multi-device programming.

The CPLDs on the Altera UP-1 circuit board are programmed via the programming software

in MAX_PLUS II and a ribbon cable called the ByteBlaster. The ByteBlaster,

shown in Figure 4.40, connects to the parallel port of a PC running MAX_PLUS II to a

10-pin male socket that complies with the JTAG standard. This standard specifies a fourwire

interface, originally developed for testing chips without removing them from a circuit

board, but can also be used to program or configure PLDs.

MAX9000, MAX7000S, and MAX7000A Programming with the ByteBlaster Cable

(By Permission of Altera Corporation)

FIGURE 4.42

JTAG Chain Device Programming and Configuration with the ByteBlaster Cable (By Permission

of Altera Corporation)

PLDs that can be programmed or configured while installed on a circuit board are

called in-system programmable (ISP) or in-circuit reconfigurable (ICR). ISP is used to

refer to nonvolatile devices, such as MAX7000S; ICR refers to volatile devices, such as

FLEX10K.

The JTAG interface has four wires, as well as power and ground connections, as

shown in Figure 4.41. Data are sent to a device from a JTAG controller (i.e., the PC) via the

TDI (Test Data In) line. Data return from the device via TDO (Test Data Out). The data

transfer is controlled by TMS (Test Mode Select). The process is driven from one step to

the next by TCK (Test Clock).

Multiple devices can be programmed in a JTAG Chain, as shown in Figure 4.42. This

connection allows both CPLDs on the Altera UP-1 Board to be programmed at the same

time. The UP-1 board also has a female 10-pin socket labeled JTAG out, which allows two

or more boards to be chained together. The choice of programming one or more CPLDs, or

146 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II

the CPLDs on one or more UP-1 boards, is determined by the placement of four on-board

jumpers. These jumper positions are explained in the Altera University Program Design

Laboratory Package User Guide. A copy of the User Guide is included in Appendix A for

reference and is available at Altera’s Web site.

The operation of the JTAG port is controlled automatically by MAX_PLUS II, so further

details are not necessary at this time. For further information on the JTAG interface,

refer to Altera Application Note 39, JTAG Boundary-Scan Testing in Altera Devices, in-

FIGURE 4.43

Hardware Setup Dialog Box

cluded in the Altera Documentation folder on the accompanying CD.

MAX_PLUS II Programmer

To program a device on the Altera UP-1 board, set the jumpers to program the EPM7128S

or configure the EPF10K20, as shown in the Altera University Program Design Laboratory

MAX_PLUS II to the 10-pin JTAG header. (You may have to run a 25-wire cable

Programmer Dialog Box

(MAX7000S Device)

4.7 • Creating a Physical Design 147

(male-D-connector-to-female-D-connector) to make it reach.) Plug an AC adapter (9-volt

dc output) into the power jack of the UP-1 board.

Open the top-level file of the project you wish to download to the UP-1 board (e.g.,

from the MAX_PLUS II menu or click the Programmer button (the icon showing the blue

ribbon cable) on the MAX_PLUS II toolbar.

If you have never programmed a device with your copy of MAX_PLUS II, you will

need to set up the hardware configuration. Click Hardware Setup in the Options menu to

FIGURE 4.45

JTAG Menu

Multi-Device JTAG Chain Setup

get the dialog box in Figure 4.43.

Select ByteBlaster in the Hardware Type box. Ensure that Parallel Port is the same

as the port the ByteBlaster is plugged into (usually LPT1:). Click OK. (If you have a

choice, configure your parallel port as an Enhanced Communications Port (ECP) in your

computer’s CMOS setup. For most users this step is not necessary, as the port is already

configured this way.)

Select Programming File Dialog Box

If the current project was compiled with the MAX7000S device selected, the pof file

for the project will automatically

be available.

The Programmer dialog

box will appear as in Figure

4.44. To download,

click Program.

If the project was

compiled for the

FLEX10K device and the

device is to be configured

via a ByteBlaster, it must

be configured via the

Multi-Device JTAG

Chain available in the

JTAG menu. Select the

JTAG menu, shown in

Figure 4.45, and choose

In the Multi-Device

shown in Figure

4.46, select the pulldown

menu for the device

name. Select

EPF10K20. Choose

Delete All to clear the

box of any previous programming

file names.

Choose the Select Programming

The Select Programming

box will appear, as in

Figure 4.47. Find and select

the file

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

Glossary 149

ote\maj_vote.sof. Click

OK. Choose the Add

button in the JTAG setup

box to add the SRAM

Object File (sof) to the

list. Choose the Detect

JTAG Chain Info button

to set up the hardware for

programming. Choose

OK. Click the Configure

button in the Programmer

dialog box to download

the binary information

to the FLEX10K

CPLD on the UP-1

board.

S U M M A R Y

shipped blank and whose function is determined by the end

user.

2. PLDs offer design flexibility, reduce board space and package

quickly than fixed-function logic.

3. Some types of PLDs include PAL (programmable array

logic), GAL (generic array logic), EPLD (erasable PLD),

CPLD (complex PLD), FPGA (field-programmable gate array).

4. Complex PLDs (CPLDs) are devices with several programmable

sections that are interconnected inside the chip.

5. PLD design and programming requires special software,

such as Altera’s MAX_PLUS II.

6. PLD designs can be entered by schematic capture (Graphic

Design Files) or text-based languages, such as Altera Hardware

Description Language (AHDL) and VHSIC Hardware

Description Language (VHDL).

7. MAX_PLUS II organizes PLD design files in a project.

Since many operations in MAX_PLUS II are performed on

a project, you should set the project to the current file (File

menu) whenever you change windows and make a modification

to a design file.

8. Save your work every time you pause for thought.

9. A MAX_PLUS II Graphic Design File (gdf) consists of

graphical symbols of components that are interconnected by

lines drawn between inputs and outputs of the components.

10. Circuit inputs and outputs in a gdf have special symbols. The

input and output pins must be named, but need not be numbered

in the first stages of a design.

11. The MAX_PLUS II compiler translates the design information

from a gdf or text file into binary data that can be downloaded

into a PLD. For a MAX7000S, the compiler generates

a Programmer Object File (pof) to program the device. For a

FLEX10K, an SRAM Object File (sof) is generated to configure

the device.

12. MAX7000S devices are nonvolatile; they stay programmed

when the power is removed from the chip. FLEX10K devices

are volatile; they lose their programming data when power is

removed.

13. If a CPLD part number is not specified, the MAX_PLUS II

compiler will automatically select one. It is good practice to

assign the part number of the device before compiling, as this

can affect the accuracy of certain parts of the design process,

such as simulation. The CPLDs on the Altera UP-1 board are

EPM7128SLC84-7 and EPF10K20RC240-4.

14. Some useful compiler options are: Design Doctor (checks

for good design practice), Timing SNF Extractor (compiles

data required for timing simulations), and Smart Recompile

(allows part of the compile process to be skipped if only part

of a design has changed).

15. Compiler messages can be in green text (Info), blue text

(Warning; possible problems, but not fatal), or red text (Error;

fatal, compiling stops).

16. MAX_PLUS II files can be arranged in a design hierarchy.

That is, a MAX_PLUS II file can contain components that

are complete MAX_PLUS II designs in and of themselves.

17. A file that contains other designs, but is not part of a higherlevel

design, is called the top level of a hierarchy.

18. If the top level of a hierarchy is a gdf, lower-level designs are

embedded in the gdf as default symbols that are created from

the original design files of the components.

19. MAX_PLUS II looks for default symbols in the present

working directory, then in the directories specified as user libraries.

20. VHDL (VHSIC Hardware Description Language) is a textbased

programming language used to model and program

digital circuits.

21. Every VHDL file requires an entity declaration, which describes

the external aspects of the design (inputs and outputs),

and an architecture body, which describes the relationship

between the inputs and outputs.

22. The entity declaration defines ports (inputs and outputs) and

the type of each port (the range of values each port can have).

23. Some common types are BIT (0 or 1), STD_LOGIC (ninevalued

standard logic), and INTEGER (whole numbers).

24. The STD_LOGIC type can take on any of the following

values:

‘X’,— — Forcing Unknown

‘0’,— — Forcing 0

‘1’,— — Forcing 1

‘Z’,— — High Impedance

‘W’,— — Weak Unknown

‘L’,— — Weak 0

‘H’,— — Weak 1

‘-’ — — Don’t care

25. STD_LOGIC is defined in a library called ieee. To use STD

LOGIC, include the following two statements at the beginning

of a file

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

26. A port in VHDL is an input or output. A signal is an internal

connection, like a wire. A variable is a piece of working

memory reserved by the VHDL file.

27. The simplest way to relate inputs and outputs in a VHDL design

is with a concurrent signal assignment statement, which

has the form: x <= (a and b) or c; The port or signal

on the left side is assigned the value of the logic expression

on the right side. (Variables are assigned with a different

operator.)

28. A port, signal, or variable can have a multiple-bit construction

of type BIT_VECTOR or STD_LOGIC_VECTOR.

These structures are called vectors and can be referred to a

separate elements (e.g., y(3) <= d(1) and d(0);) or

as a group (e.g., y <= “1000”).

29. A selected signal assignment statement can act as a truth

table in VHDL. It assigns alternative values to one or more

outputs, depending on the alternative values on one or more

inputs.

30. VHDL constructs and statements can be selected in generic

31. VHDL designs can be embedded in a gdf as default symbols.

32. Pin numbers must be assigned to a design before it can be

downloaded to a CPLD. Pins can be assigned in the Pin/ Location/

Chip dialog box (accessed by highlighting a pin symbol

and right-clicking) or by editing the project’s Assignment

and Configuration File (acf).

33. An Altera CPLD can be programmed directly from a PC parallel

port via a ByteBlaster cable.

34. The ByteBlaster cable implements a programming interface

specified by a standard (IEEE Std. 1149.1) of the Joint Test

Action Group (JTAG).

35. A JTAG port is a 4-wire interface for loading test and

programming information into one or more JTAG-compliant

devices. It consists of an input (TDI), output (TDO), mode

select (TMS), and clock (TCK).

G L O S S A R Y

AHDL (Altera Hardware Description Language) Altera’s

proprietary text-entry design tool for PLDs.

Program Design Laboratory Package, containing two

CPLDs and a number of input and output devices.

Architecture AVHDL structure than defines the relationship

between input, output, and internal signals or variables in a design.

circuits that are constructed for a specific design purpose. The

term could refer to a PLD, although it usually means a customdesigned

fixed function device.

file that contains information about the configuration options for

a project, including assigned device and pin numbers.

Bit string literal A group of bits assigned to the elements of a

vector, enclosed in double quotes (e.g., “001011”).

program or configure Altera CPLDs via the parallel port (LPT

port) of an IBM PC or compatible.

Comment Explanatory text in a VHDL (or other computer

language) file that is ignored by the computer at compile time.

design information (such as a drawing or text file) and create

required programming information for a CPLD.

Complex PLD (CPLD) A digital device consisting of several

programmable sections with internal interconnections between

the sections.

Concurrent Simultaneous.

Concurrent signal assignment A relationship between an input

and output port or signal in which the output is changed as

soon as there is a change in input. If the file has more than one

concurrent signal assignment, they are all evaluated simultaneously.

as a block, showing only the design’s inputs and outputs.

The symbol can be used as a component in any Graphic Design

File.

the design requirements of a PLD. Design entry can be done by

entering a schematic or a text file that describes the required digital

function.

and programming software.

of a design.

output pins, for a PLD design.

digital design is entered as a schematic.

to design digital circuits by entering text-based descriptions of

the circuits.

Hierarchical design A PLD design that is ordered in layers or

levels. The highest level of design contains components that are

themselves complete designs. These components may, in turn,

have lower-level designs embedded within them.

a FLEX10K) to be configured without removing it from a circuit

board.

IEEE Standard 1164 The standard which defines a variety of

VHDL types and operations, including the STD_LOGIC and

STD_LOGIC_VECTOR types.

ISP In-system programmability. The ability of a PLD (such as

a MAX7000S) to be programmed without removing it from a

circuit board.

JTAG Joint Test Action Group. A standards body that developed

the format (called IEEE Std. 1149.1) for testing and programming

devices while they are installed in a system.

Problems 151

and TDO ports form a continuous chain connection. Such a

chain allows multi-device programming.

Library A collection of VHDL design units that have been

previously compiled.

owned by Altera Corporation.

removed.

by more than one VHDL file.

entity.

that can be programmed by the user to implement any digital

logic function.

Programmer Object File (pof) Binary file used to program a

PLD of the Altera MAX series.