Chapter 1 Basic Principles of Digital Systems outlin e 1

diode (LED) or liquid crystal display (LCD) elements, shaped like a figure-8,

which can be used to display decimal digits and other characters by turning on the

appropriate elements.

the LEDs are connected to the circuit supply voltage. Each segment is illuminated

by a logic LOW at its cathode.

Common cathode display A seven-segment display in which the cathodes of all

LEDs are connected together and grounded. A logic HIGH illuminates a segment

when applied to its anode.

Display

The seven-segment display, shown in Figure 5.22, is a numerical display device used to

show digital circuit outputs as decimal digits (and sometimes hexadecimal digits or other

alphabetic characters). It is called a seven-segment display because it consists of seven luminous

segments, usually LEDs or liquid crystals, arranged in a figure-8. We can display

any decimal digit by turning on the appropriate elements, designated by lowercase letters,

around the display, ending with g as the center element.

Figure 5.23 shows the usual convention for decimal digit display. Some variation

from this convention is possible. For example, we could have drawn the digits 6 and 9

with “tails” (i.e., with segment a illuminated for 6 or segment d for 9). By convention, we

K E Y T E R M S

➥ decode4g.rpt

b

a

c

f

g

FIGURE 5.22

Seven-segment Numerical

Display

display digit 1 by illuminating segments b and c, although segments e and f would also

work.

The electrical requirements for an LED circuit are simple. Since an LED is a diode, it

decoder/driver for an LED display will illuminate an element by completing this circuit, either

by supplying VCC or ground. A series resistor limits the current to prevent the diode

from burning out and to regulate its brightness. If the anode is _5 volts with respect to

cathode, the resistor value should be in the range of 220 _ to 470 _.

FIGURE 5.23

Convention for Displaying Decimal Digits

Vcc a b c Vcc

a b c

Electrical Requirements for LED Displays

Seven-segment displays are configured as common anode or common cathode, as

shown in Figures 5.24b and c. In a common cathode display, the cathodes of all LEDs are

connected together and brought out to one or more pin connections on the display package.

The cathode pins are wired externally to the circuit ground. We illuminate the segments by

applying logic HIGHs to individual anodes.

Similarly, the common anode display has the anodes of the segments brought out to

one or more common pins. These pins must be tied to the circuit power supply (VCC).

The segments illuminate when a decoder/driver makes their individual cathodes LOW.

Figure 5.25 shows how the diodes could be physically laid out in a common anode display.

The two types of displays allow the use of either active HIGH or active LOW circuits

to drive the LEDs, thus giving the designer some flexibility. However, it should be noted

that the majority of seven-segment decoders are for common-anode displays.

❘❙❚ EXAMPLE 5.4 Sketch the segment patterns required to display all 16 hexadecimal digits on a sevensegment

display. What changes from the patterns in Figure 5.23 need to be made?

Solution The segment patterns are shown in Figure 5.26.

Hex digits B and D must be displayed as lowercase letters, b and d, to avoid confusion

between B and 8 and between D and 0. To make 6 distinct from b, 6 must be given a tail

(segment a) and to make 6 and 9 symmetrical, 9 should also have a tail (segment d). ❘❙❚

number is represented by a 4-bit binary number (e.g., 905 (decimal) _ 1001 0000

0101 (BCD)).

A BCD-to-seven-segment decoder is a circuit with a 4-bit input for a BCD digit and

seven outputs for segment selection. To display a number, the decoder must translate the

input bits to a combination of active outputs. For example, the input digit D3D2D1D0 _

0000 must illuminate segments a, b, c, d, e, and f to display the digit 0. We can make a truth

K E Y T E R M S

Vcc

a

b

d

e

g

FIGURE 5.25

Physical Placement of LEDs in a

Common Anode Display

Hexadecimal Digit Display Format

table for each of the outputs, showing which must be active for every digitwewish to display.

The truth table for a common-anode decoder (activeLOWoutputs) is given inTable 5.3.

The illumination of each segment is determined by a Boolean function of the input

variables, D3D2D1D0. From the truth table, the function for segment a is

a _ D_3D_2D_1D0 _ D_3D2D_1D_0 _ D_3D2D1D_0

(Since the display is active-LOW, this means segment a is OFF for digits 1, 4, and 6.)

If we assume that inputs 1010 to 1111 are never going to be used (“don’t care states”,

symbolized by X), we can make any of these states produce HIGH or LOW outputs, depending

on which is most convenient for simplifying the segment functions. Figure 5.27a

shows a Karnaugh map simplification for segment a. The resultant function is

The corresponding partial decoder is shown in Figure 5.27b.

We could do a similar analysis for each of the other segments, but if we are programming

the decoder function into a CPLD, it is just as simple to write the truth table directly

into a selected signal assignment statement, as shown in the VHDL code that follows.

—— bcd_7seg.vhd

—— BCD-to-seven-segment decoder

ENTITY bcd_7seg IS

PORT(

d3, d2, d1, d0 : IN BIT;

END bcd_7seg;

ARCHITECTURE seven_segment OF bcd_7seg IS

SIGNAL input : BIT_VECTOR (3 downto 0);

SIGNAL output: BIT_VECTOR (6 DOWNTO 0);

BEGIN

WITH input SELECT

output <= “0000001” WHEN “0000”,

“1001111” WHEN “0001”,

0 0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 1 1 0 0 1 1 1 1

2 0 0 1 0 0 0 1 0 0 1 0

3 0 0 1 1 0 0 0 0 1 1 0

4 0 1 0 0 1 0 0 1 1 0 0

5 0 1 0 1 0 1 0 0 1 0 0

6 0 1 1 0 1 1 0 0 0 0 0

7 0 1 1 1 0 0 0 1 1 1 1

8 1 0 0 0 0 0 0 0 0 0 0

9 1 0 0 1 0 0 0 1 1 0 0

1 0 1 0 X X X X X X X

1 0 1 1 X X X X X X X

Invalid Range 1 1 0 0 X X X X X X X

1 1 0 1 X X X X X X X

1 1 1 0 X X X X X X X

1 1 1 1 X X X X X X X

➥ bcd_7seg.vhd

“0010010” WHEN “0010”,

“0000110” WHEN “0011”,

“1001100” WHEN “0100”,

“0100100” WHEN “0101”,

“1100000” WHEN “0110”,

“0001111” WHEN “0111”,

“0000000” WHEN “1000”,

“0001100” WHEN “1001”,

“1111111” WHEN others;

—— Separate the output vector to make individual pin outputs.

a <= output(6);

b <= output(5);

c <= output(4);

d <= output(3);

e <= output(2);

f <= output(1);

g <= output(0);

END seven_segment;

a

D2

D0

D3

Segment a

00

D3D2

00 01 11 10

01

11

10

1 0 0 1

0 0 X X

Decoding Segment a

The inputs D3D2D1D0 are defined separately, then concatenated (linked in sequence)

by the & operator to make a BIT_VECTOR called input. This is equivalent to the following

four concurrent signal assignments:

input (3) <= d3;

input (2) <= d2;

input (1) <= d1;

input (0) <= d0;

176 C H A P T E R 5 • Combinational Logic Functions

Why not simply define d as a vector? If we wish to create a graphic symbol for the

seven-segment decoder, the above method creates a symbol shown with four separate inputs,

rather than a single thick line for a 4-bit bus input. The design will work either way.

For each value of input, a signal assignment defines the output vector, each bit of

which represents the value of one segment. For example, the first clause (“0000001”

WHEN “0000”) sets all segments ON except segment g, thus displaying the digit “0”.

As a variation, we could define a signal called d_inputs of type INTEGER with

RANGE 0 to 9. The WHEN clauses would evaluate the integer values 0 to 9, as follows.

WITH d_inputs SELECT

output <= “0000001” WHEN 0,

“1001111” WHEN 1,

“0010010” WHEN 2,

“0000110” WHEN 3,

“1001100” WHEN 4,

“0100100” WHEN 5,

“0100000” WHEN 6,

“0001111” WHEN 7,

“0000000” WHEN 8,

“0000100” WHEN 9,

“1111111” WHEN others; — — blank

Ripple Blanking

Ripple blanking A technique used in a multiple-digit numerical display that suppresses

leading or trailing zeros in the display, but allows internal zeros to be displayed.

is a change in a signal in its sensitivity list.

determine whether the PROCESS should be executed.

be executed, depending on the value of a signal or variable.

if a Boolean test condition is true.

A feature often included in seven-segment decoders is ripple blanking. The ripple blanking

feature allows for suppression of leading or trailing zeros in a multiple digit display,

while allowing zeros to be displayed in the middle of a number.

Each display decoder has a ripple blanking input (R_B_I_) and a ripple blanking output

(R_B_O_), which are connected in cascade, as shown in Figure 5.28. If the decoder input

D3D2D1D0 is 0000, it displays digit 0 if R_B_I_ _ 1 and shows a blank if R_B_I_ _ 0.

If R_B_I_ _ 1 OR D3D2D1D0 is (NOT 0000), then R_B_O_ _ 1. When we cascade two or

more displays, these conditions suppress leading or trailing zeros (but not both) and still

display internal zeros.

To suppress leading zeros in a display, ground the R_B_I_ of the most significant digit

decoder and connect the R_B_O_ of each decoder to the R_B_I_ of the next least significant digit.

Any zeros preceding the first nonzero digit (9 in this case) will be blanked, as R_B_I_ _ 0

AND D3D2D1D0 _ 0000 for each of these decoders. The 0 inside the number 904 is

displayed since its R_B_I_ _ 1.

K E Y T E R M S

Trailing zeros are suppressed by reversing the order of R_B_I_ and R_B_O_ from the above

example. R_B_I_ is grounded for the least significant digit and the R_B_O_ for each decoder cascades

to the R_B_I_ of the next most significant digit.

We can implement the ripple blanking feature in a VHDL file by modifying the file

for a standard BCD- or hexadecimal-to-seven-segment decoder to include a CASE statement

within a PROCESS. A PROCESS is a construct containing statements that are executed

if a signal in the sensitivity list of the PROCESS changes. The general form of a

PROCESS is:

PROCESS (sensitivity list)

BEGIN

statements;

A CASE statement can be one of the constructs used inside a process if we want to select

among several alternatives. It takes the following form:

FIGURE 5.28

Zero Suppression in Seven-segment Displays

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

—— CASE statement within a PROCESS

PROCESS (__signal_name, __signal_name, __signal_name)

BEGIN

WHEN __constant_value =>

__statement;

__statement;

WHEN __constant_value =>

__statement;

__statement;

WHEN OTHERS =>

__statement;

__statement;

END CASE;

END PROCESS;

Whether the digit “0” is displayed or suppressed is conditional upon the value ofR_B_I_. This can

be tested by an IF statement within the PROCESS. An IF statement executes one or more

VHDLstatements, depending on the state of a test condition. It has the following syntax.

IF __expression THEN

__statement;

__statement;

ELSIF __expression THEN

__statement;

__statement;

ELSE

__statement;

END IF;

The following VHDL code demonstrates the ripple blanking function.

ENTITY sevsegrb IS

PORT(

nRBI, d3, d2, d1, d0 : IN BIT;

END sevsegrb;

ARCHITECTURE seven_segment OF sevsegrb IS

SIGNAL input: BIT_VECTOR (3 DOWNTO 0);

SIGNAL output: BIT_VECTOR (6 DOWNTO 0);

BEGIN

—— Process Statement

PROCESS (input, nRBI)

BEGIN

— — 0 suppressed

output <= “1111111”;

nRBO <= ‘0’;

ELSIF (input = “0000” and nRBI = ‘1’) THEN

— — 0 displayed

output <= “0000001”;

nRBO <= ‘1’;

ELSE

CASE input IS

➥ sevsegrb.vhd

WHEN “0010” => output <= “0010010”; —— 2

WHEN “0011” => output <= “0000110”; —— 3

WHEN “0100” => output <= “1001100”; —— 4

WHEN “0101” => output <= “0100100”; —— 5

WHEN “0110” => output <= “0100000”; —— 6

WHEN “0111” => output <= “0001111”; —— 7

WHEN “1000” => output <= “0000000”; —— 8

WHEN “1001” => output <= “0000100”; —— 9

WHEN others => output <= “1111111”; —— blank

END CASE;

nRBO <= ‘1’;

END IF;

–— Separate the output vector to make individual pin outputs.

b <= output(5);

c <= output(4);

d <= output(3);

e <= output(2);

f <= output(1);

g <= output(0);

END PROCESS;

END seven_segment;

❘❙❚ SECTION 5.1C REVIEW PROBLEM

5.3 When would it be logical to suppress trailing zeros in a multiple-digit display and

when should trailing zeros be displayed?

more active input lines.

to the subscript of the active input having the highest priority. This is usually

defined as the input with the largest subscript value.

The function of a digital encoder is complementary to that of a digital decoder. A decoder

activates a specified output for a unique digital input code. An encoder operates in the reverse

direction, producing a particular digital code (e.g., a binary or BCD number) at its

outputs when a specific input is activated.

Figure 5.29 shows an 3-bit binary encoder. The circuit generates a unique 3-bit binary

output for every active input provided only one input is active at a time.

The encoder has only 8 permitted input states out of a possible 256. Table 5.4 shows

the allowable input states, which yield the Boolean equations used to design the encoder.

These Boolean equations are:

The D0 input is not connected to any of the encoding gates, since all outputs are in

their LOW (inactive) state when the 000 code is selected.

K E Y T E R M S

Priority Encoder

The shortcoming of the encoder circuit shown in Figure 5.29 is that it can generate wrong

codes if more than one input is active at the same time. For example, if we make D3 and D5

HIGH at the same time, the output is neither 011 or 101, but 111; the output code does not

correspond to either active input.

One solution to this problem is to assign a priority level to each input and, if two or

more are active, make the output code correspond to the highest-priority input. This is

called a priority encoder. Highest priority is assigned to the input whose subscript has the

largest numerical value.

❘❙❚ EXAMPLE 5.5 Figures 5.30a through c show a priority encoder with three different combinations of inputs.

Determine the resultant output code for each figure. Inputs and outputs are active

HIGH.

FIGURE 5.29

3-bit Encoder (No Input Priority)

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 1 0 0 1 0

0 0 0 0 1 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 1 0 0 0 0 1 0 1

0 1 0 0 0 0 0 1 1 0

Example 5.5

Priority Encoder Inputs

5.2 • Encoders 181

Solution

Figure 5.30a: The highest-priority active input is D5. D4 and D1 are ignored. Q2Q1Q0

_ 101.

❘❙❚

change the code resulting from a higher-priority input.

For example, if inputs D3 and D5 are both active, the correct output code is Q2Q1Q0 _ 101.

The code for D3 would be Q2Q1Q0 _ 011. Thus, D3 must not make Q1 _ 1. The Boolean

expressions for Q2, Q1, and Q0 covering only these two codes are:

Q2 _ D5 (HIGH if D5 is active.)

Q1 _ D3D_5 (HIGH if D3 is active AND D5 is NOT active.)

Q0 _ D3 _ D5 (HIGH if D3 OR D5 is active.)

The truth table of an 3-bit priority encoder is shown in Table 5.5.

N O T E

Table 5.5 Truth Table for an 3-bit Priority Encoder

D7 D6 D5 D4 D3 D2 D1 Q2 Q1 Q0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 1 X 0 1 0

0 0 0 0 1 X X 0 1 1

0 0 0 1 X X X 1 0 0

0 0 1 X X X X 1 0 1

0 1 X X X X X 1 1 0

Corresponding Decimal Values

1 1 1 7

1 0 1 5

0 1 1 3

0 0 1 1

Restating the encoding principle, a bit goes HIGH if it is part of the code for an active

input AND it is NOT kept LOW by an input with a higher priority. We can use this principle

to develop a mechanical method for generating the Boolean equations of the outputs.

1. Write the codes in order from highest to lowest priority, as in Table 5.6.

182 C H A P T E R 5 • Combinational Logic Functions

2. Examine each code. For a code with value n, add a Dn term to each Q equation where

there is a 1. For example, for code 111, add the term D7 to the equations for Q2, Q1, and

Q0. For code 110, add the term D6 to the equations for Q2 and Q1. (Steps 1 and 2 generate

the nonpriority encoder equations listed earlier.)

3. Modify any Dn terms to ensure correct priority. Every time you write a Dn term, look at

the previous lines in the table. For each previous code with a 0 in the same column as

the 1 that generates Dn, use an AND function to combine Dn with a corresponding D_.

For example, code 101 generates a D5 term in the equations for Q2 and Q0. The term in

the Q2 equation need not be modified because there are no previous codes with a 0 in

the same column. The term in the Q0 equation must be modified since there is a 0 in the

The equations from the 3-bit encoder of Figure 5.29 are modified by the priority encoding

principle as follows:

Q2 _ D7 _ D6 _ D5 _ D4

Q1 _ D7 _ D6 _ D_5D_4D3 _ D_5D_4D2

Q0 _ D7 _ D_6D5 _ D_6D_4D3 _ D_6D_4D_2D1

VHDL Priority Encoder

The most obviousway to program a priority encoder inVHDLis to use the equations derived

in the previous section in a set of concurrent signal assignment statements, as follows.

—— hi_pri8a.vhd

ENTITY hi_pri8a IS

PORT(

d : IN BIT_VECTOR(7 downto 0);

END hi_pri8a;

ARCHITECTURE a OF hi_pri8a IS

BEGIN

q(2) <= d(7) or d(6) or d(5) or d(4);

q(1) <= d(7) or d(6)

or ((not d(5)) and (not d(4)) and d(3))

or ((not d(5)) and (not d(4)) and d(2));

q(0) <= d(7) or ((not d(6)) and d(5))

or ((not d(6)) and (not d(4)) and d(3))

or ((not d(6)) and (not d(4)) and (not d(2)) and d(1));

END a;

Although this code works, it is not terribly elegant, nor does it give any insight into the

the equations become more cumbersome with each new bit and soon become impractically

large and susceptible to typing errors. A VHDL conditional signal assignment statement is

an ideal alternative for use in a priority encoder circuit. A section of VHDL code using this

format is shown below.

–— hi_pri8b.vhd

ENTITY hi_pri8b IS

PORT(

q : OUT INTEGER RANGE 0 to 7);

END hi_pri8b;

➥ hi_pri8a.vhd

➥ hi_pri8b.vhd