• Magnitude Comparators 205

ELSIF a=b THEN

compare <= “101”;

ELSIF a>b THEN

compare <= “011”;

ELSE

compare <= “111”;

agtb <= compare(2);

aeqb <= compare(1);

altb <= compare(0);

END PROCESS;

END a;

5.6 Parity Generators and Checkers

the number of 1s.

even number of 1s.

odd number of 1s.

odd, depending on the type of parity.

When data are transmitted from one device to another, it is necessary to have a system of

checking for errors in transmission. These errors, which appear as incorrect bits, occur as a

result of electrical limitations such as line capacitance or induced noise.

K E Y T E R M S

➥ compare8.vhd

5.6 • Parity Generators and Checkers 209

Parity error checking is a way of encoding information about the correctness of data

before they are transmitted. The data can then be verified at the system’s receiving end.

Figure 5.63 shows a block diagram of a parity error-checking system.

The parity generator in Figure 5.63 examines the outgoing data and adds a bit called

the parity bit that makes the number of 1s in the transmitted data odd or even, depending

on the type of parity. Data with EVEN parity have an even number of 1s, including the

parity bit, and data with ODD parity have an odd number of 1s.

The data receiver “knows” whether to expect EVEN or ODD parity. If the incoming

number of 1s matches the expected parity, the parity checker responds by indicating that

correct data have been received. Otherwise, the parity checker indicates an error.

❘❙❚ EXAMPLE 5.16 Data are transmitted from a PC serial port to a modem in groups of 7 data bits plus a parity

bit. What should the parity bit, P, be for each of the following data if the parity is EVEN?

If the parity is ODD?

a. 0110110

b. 1000000

c. 0010101

a. 0110110 Four 1s in data. (4 is an even number.)

EVEN parity: P _ 0

ODD parity: P _ 1

b. 1000000 One 1 in data. (1 is an odd number.)

EVEN parity: P _ 1

ODD parity: P _ 0

c. 0010101 Three 1s in data. (3 is an odd number.)

EVEN parity: P _ 1

ODD parity: P _ 0

❘❙❚

An Exclusive OR gate can be used as a parity generator or a parity checker. Figure

XOR truth table has an even number of 1s if we include the output column.

Figure 5.65 shows the block diagram of a circuit that will generate an EVEN parity bit

from 2 data bits, A and B, and transmit the three bits one after the other, that is, serially, to

a data receiver.

FIGURE 5.63

Parity Error Checking

Exclusive OR Gate

Figure 5.66 shows a parity checker for the parity generator in Figure 5.65. Data are received

serially, but read in parallel. The parity bit is re-created from the received values of

A and B, and then compared to the received value of P to give an error indication, P_. If P

and A _ B are the same, then P_ _ 0 and the transmission is correct. If P and A _ B are

different, then P_ _ 1 and there has been an error in transmission.

❘❙❚ EXAMPLE 5.17 The following data and parity bits are transmitted four times: ABP _ 101.

1. State the type of parity used.

2. The transmission line over which the data are transmitted is particularly noisy and the

data arrive differently each time as follows:

a. ABP _ 101

b. ABP _ 100

c. ABP _ 111

d. ABP _ 110

Indicate the output P_ of the parity checker in Figure 5.66 for each case and state what

the output means.

Solution

1. The system is using EVEN parity.

2. The parity checker produces the following responses:

a. ABP _ 101

b. ABP _ 100

c. ABP _ 111

OR Truth Table

0 0 0

1 0 1

Even Parity Generation

Even Parity Checking

d. ABP _ 110

incorrectly received.)

❘❙❚

The second and third cases in Example 5.17 show that parity error-detection cannot

The fourth case points out the major flaw of parity error detection: An even number of

errors cannot be detected. This is true whether the parity is EVEN or ODD. If a group of

bits has an even number of 1s, a single error will change that to an odd number of 1s, but a

double error will change it back to even. (Try a few examples to convince yourself this is

true.)

than an Exclusive OR, gate. If a set of transmitted data bits require a 1 for EVEN parity, it

follows that they require a 0 for ODD parity. This implies that EVEN and ODD parity generators

must have opposite-sense outputs.

❘❙❚ EXAMPLE 5.18 Modify the circuits in Figures 5.65 and 5.66 to operate with ODD parity. Verify their operation

with the data bits AB _ 11 transmitted twice and received once as AB _ 11 and once

as AB _ 01.

Solution Figure 5.67a shows an ODD parity generator and Figure 5.67b shows an ODD

parity checker. The checker circuit still has an Exclusive OR output since it presents the

same error codes as an EVEN parity checker. The parity bit is re-created at the receive end

of the transmission path and compared with the received parity bit. If they are the same,

Data: AB _ 11 Parity: P _ A_____B_ _ 1_____1_ _ 1

Received data: AB _ 11

Example 5.18

ODD Parity Generator and Checker

212 C H A P T E R 5 • Combinational Logic Functions

Generator:

Data: AB _ 11 Parity: P _ A_____B_ _ 1_____1_ _ 1

Received data: AB _ 01

❘❙❚

XOR gate for each pair of bits and combining the gate outputs in further stages of 2-input

XOR gates. The true form of the generated parity bit is PE, the EVEN parity bit. The complement

form of the bit is PO, the ODD parity bit.

Table 5.13 shows the XOR truth table for 4 data bits and the ODD and EVEN parity

bits. The EVEN parity bit PE is given by (A _ B) _ (C _ D). The ODD parity bit

of 1s.

and check either EVEN or ODD parity, depending on the state of one select input.

0 0 0 0 0 0 0 1

0 0 0 1 0 1 1 0

0 0 1 0 0 1 1 0

0 0 1 1 0 0 0 1

0 1 0 0 1 0 1 0

0 1 0 1 1 1 0 1

0 1 1 0 1 1 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 0 1

1 0 1 1 1 0 1 0

1 1 0 0 0 0 0 1

1 1 0 1 0 1 1 0

1 1 1 0 0 1 1 0

1 1 1 1 0 0 0 1

FIGURE 5.68

Example 5.19

4-bit Parity Generator

5.6 • Parity Generators and Checkers 213

❘❙❚ EXAMPLE 5.20 Draw the circuit for an 8-bit EVEN/ODD parity generator.

previous example. The circuit is shown in Figure 5.70.

❘❙❚

❘❙❚ SECTION 5.6 REVIEW PROBLEM

parity. Which of the following data do we know are incorrect? Could there be errors in

the remaining data? Explain.

a. 010010

b. 011010

c. 1110111

d. 1010111

e. 1000101

output is configured as a programmable inverter to give PE or PO. When E_V_E_N_/ODD _ 0,

the parity output is not inverted and the circuit generates PE. When E_V_E_N_/ODD _ 1, the

FIGURE 5.69

Example 5.19

4-bit Parity Checker

FIGURE 5.70

Example 5.20

8-bit Parity Generator

214 C H A P T E R 5 • Combinational Logic Functions

S U M M A R Y

1. A decoder detects the presence of a particular binary code.

The simplest decoder is an AND or NAND gate, which can

detect a binary code when combined with the right combination

of input inverters.

2. Multiple-output decoders are implemented by a series of single-

gate decoders, each of which responds to a different input

code.

3. For an n-input decoder, there can be as many as 2n unique

4. MAX_PLUS II can simulate the function of a digital circuit

by generating a set of output waveforms in response to a defined

set of input waveforms.

5. VHDL constructs such as selected signal assignment statements

and conditional signal assignments can describe decoders.

Both statement types assign alternative values to a

VHDL port or signal, based on the state of another port or

signal.

6. A selected signal assignment statement has the form:

__signal ____expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value;

7. A conditional signal assignment statement has the form:

__signal __ __expression WHEN __boolean_expression ELSE

__expression WHEN __boolean_expression ELSE

__expression;

8. SIGNALs act as internal connections in a VHDL design entity.

They can be single lines or vectors and are declared before

the BEGIN clause of an ARCHITECTURE body.

9. The report file of a MAX_PLUS II project contains design

and configuration information, including the Boolean equations

that the compiler derives from the design entry file(s) of

the project.

10. A seven-segment display is an array of seven luminous segments

(usually LED or LCD), arranged in a figure-8 pattern,

used to display numerical digits.

11. The segments in a seven-segment display are designated by

lowercase letters a through g. The sequence of labels goes

clockwise, starting with segment a at the top and ending with

12. Seven-segment displays are configured as common anode

(active-LOW inputs) or common cathode (active-HIGH segments).

13. A seven-segment decoder can be described with a truth table

or Boolean equation for each segment function. Since the

segment functions do not simplify very much, it is often easier

to program a CPLD with a VHDL truth table, in the form

of a selected signal assignment statement, rather than with

the Boolean equations of the decoder.

14. A multiplexer (MUX) is a circuit that directs a signal or

group of signals (called the data inputs) to an output, based

on the status of a set of select inputs.

15. Generally, for n select inputs in a multiplexer, there arem_2n

data inputs. Such a multiplexer is referred to as an m-to-1

multiplexer.

16. The selected data input in a MUX is usually denoted by a

subscript that is the decimal equivalent of the combined binary

value of the select inputs. For example, if the select inputs

in an 8-to-1 MUX are set to S2S1S0 _ 100, data input D4

is selected since 100 (binary) _ 4 (decimal).

17. A MUX can be designed to switch groups of signals to a

multi-bit output. The inputs can be denoted by double subscript

notation, where the first subscript indicates the number

of the signal group and the second subscript the element

in the group. For example, a MUX can have a 4-bit

set of inputs called D03D02D01D00 and another 4-bit input

group called D13D12D11D10, each of which can be

switched to a 4-bit output called Y3Y2Y1Y0 by the state of

one select input.

18. A multiplexer can be used in time-dependent applications if

a binary counter is applied to its select inputs.

19. Some examples of time-dependent MUX applications are

waveform or bit pattern generation and time-division multiplexing

(TDM).

single transmission path by allotting a time slot for every signal,

during which that signal has sole access to the transmission

path.

channel transmits one bit each time it is selected, or byte (or

word) multiplexing, in which a channel transmits and entire

byte or word each time it is selected.

22. A demultiplexer (DMUX) receives data from a single source

and directs the data to one of several outputs, which is selected

by the status of a set of select inputs.

23. A decoder with an enable input can also act as a demultiplexer

if the enable input of the decoder is used as a data input

for a demultiplexer.

24. A TDM signal can be demultiplexed by applying a binary

count to the DMUX’s select inputs at the same rate as the

count is applied to the select input of the multiplexer that

originally sent the data.

25. A CMOS analog multiplexer or demultiplexer works by using

a decoder to enable a set of analog data transmission

switches. It can be used in either direction.

26. A magnitude comparator determines whether two binary

numbers are equal and, if not, which one is greater.

27. The simplest equality comparator is an XNOR gate, whose

output is HIGH if both inputs are the same.

28. A pair of multiple-bit numbers can be compared by a set of

XNOR gates whose outputs are ANDed. The circuit compares

the two numbers bit-by-bit.

29. Given two numbers A and B, the Boolean function A_nBn,

if true, indicates that the nth bit of A is less than the nth

bit of B.

30. Given two numbers A and B, the Boolean function AnB_n,

if true, indicates that the nth bit of A is greater than the nth

bit of B.

❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚❘❙❚

31. The less-than and greater-than functions can be combined

with an equality comparator to determine, bit-by-bit, how

two numbers compare in magnitude to one another.

32. A magnitude comparator can be best implemented in VHDL

by using INTEGER types for the inputs and using IF statements

to compare their respective magnitudes.

33. Parity checking is a system of error detection that works by

counting the number of 1s in a group of bits.

34. Even parity requires a group of bits to have an even number

of 1s. Odd parity requires a group of bits to have an odd number

of 1s. This is achieved by appending a parity bit to

the data whose value depends on the number of 1s in the

data bits.

35. An XOR gate is the simplest even parity generator. Each line

in its truth table has an even number of 1s, if the output column

is included.

36. An XNOR gate can be used to generate an odd parity bit

from two data bits.

37. A parity checker consists of a parity generator on the receive

end of a transmission system and a comparator to determine

if the locally generated parity bit is the same as the transmitted

parity bit.

38. Parity generators and checkers can be expanded to any number

of bits by using an XOR gate for each pair of bits and

combining the gate outputs in further stages of 2-input XOR

gates.

Glossary 215