Development Tools Are Key for fpga soCs
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Development Tools Are Key for FPGA SoCsA new generation of chips that combine standard CPU architectures with programmable logic fabrics offer unique opportunities. They also present a challenge of bringing together two disciplines that must now focus on the same device. by Matt Spexarth, National Instruments Embedded designers have practiced heterogeneous computing by combining microprocessors and FPGAs within embedded systems since the advent of commercially viable FPGAs. FPGAs initially acted primarily as glue logic that interfaced processing systems, peripherals, and I/O. As FPGA technology improved, the FPGA market expanded to take a larger and more central role in some embedded systems. FPGA vendors began embedding hard microcontroller and microprocessor IP into FPGA-centric chips nearly a decade ago. More common today, soft microcontroller IP is often integrated into FPGA-based designs. The latest trend in heterogeneous computing is integrating processor and FPGA subsystems into a single system-on-chip (SoC). Processor and software centric design teams require new tools to take advantage of both systems on these complex SoCs. System designers find the combination of processor and FPGA attractive for embedded systems because of the wide flexibility it offers in a standard design template. Essentially, the processor and FPGA work together to overcome the weaknesses in each element when they stand alone. The processor in the system provides a wide range of standard peripheral interfaces: Ethernet, serial, USB, CAN, SPI, memory, and more. In a processor-only approach, application-specific I/O is typically interfaced via one or more peripheral interfaces, such as SPI or USB. Developing software for the processor is widely understood and manageable by a large population of software engineers using standard tools, development languages, and operating systems. Once a processor is chosen, the possible interfaces to I/O are fixed and the system becomes rigid. Placing an FPGA between the processor and the application-specific I/O boosts the flexibility and processing capability of the overall system. An FPGA between the processing system and the I/O provides a reconfigurable I/O (RIO) architecture that can serve as a co-processing engine, inline signal processor, safety subsystem, or extremely low-latency control system. The reconfigurable nature of the FPGA provides a mechanism for hardware upgrades and product differentiation, which extend product life in a world of evolving interfaces and standards (Figure 1). Despite the many advantages in a standardized hardware topology of processor and FPGA, this combination presents some challenges. These include the extra power consumed by the additional FPGA target; the size, cost, and complexity of integrating a separate FPGA into PCB design; and the programming challenges associated with FPGA hardware design compared to software development on processors. FPGA vendors are addressing many of these challenges head on. Thanks to increasing cost pressures associated with shrinking feature size on ASICs and custom SoCs, FPGA vendors have developed general-purpose, processor-focused SoCs with programmable logic that can be customized to meet specific application needs. The Xilinx Zynq All Programmable SoC integrates an ARM Cortex-A9 processing subsystem with FPGA logic (Figure 2). The Cypress Semiconductor PSoC (Programmable SoC) and the Microsemi SmartFusion cSoC (customizable SoC) integrate ARM Cortex-M3 processing units with programmable logic and programmable analog interfaces. Altera has also announced a series of SoC FPGA devices based on ARM Cortex-A9 processors with FPGA fabric. These products reduce the size, cost, and power of incorporating an FPGA in an embedded system, potentially making a programmable logic standard in a wide range of applications. In addition, a series of SoC FPGA devices at different performance levels can replace hundreds of custom ASICs to create an attractive economy of scale. Software Programming AND Hardware Description LanguagesIntegrating the FPGA subsystem into a processor SoC removes most of the hardware PCB design concerns of integrating similar functionality via a discrete processor and discrete FPGA. The final hurdle in the development process is programming the two subsystems. Digital hardware designers cringe at the use of the word “programming” in reference to the FPGA subsystem because an FPGA isn’t simply programmed. The FPGA subsystem is an electronic circuit, and it is designed as hardware. Typically, hardware description languages (HDLs) such as VHDL or Verilog are necessary to take advantage of the FPGA. Teams who have used FPGAs in the past likely already have HDL expertise, but design teams interested in taking advantage of an SoC with FPGA fabric now have a new challenge. The pool of system designers who are fluent in processor programming languages, such as C/C++, is abundant. However, HDL experts represent a small fraction of the embedded system engineer workforce compared to software engineers. Managers must assemble a coordinated team that includes both software engineers and digital designers working in tandem to realize the full potential of the heterogeneous architecture on the processor and FPGA SoC architecture. If programmable logic tools do not evolve to better suit the skills of the large embedded software engineering contingency, FPGAs and SoCs with FPGA fabric will continue to serve only the niches that FPGAs have carved today. For maximum adoption of these SoCs, FPGA vendors are investing heavily in tools and partners to better align the development practices between processors and FPGA fabric. High- level synthesis (HLS) tools, such as the LabView FPGA Module, Vivado HLS or SystemC, reduce the gap in code development between software and digital domains. LabView is a high-level tool used for both processor and FPGA system design. In 2003, National Instruments released a plug-in module for LabView to target NI FPGA-based hardware that includes Xilinx FPGAs. The LabView FPGA Module uses Xilinx compile tools in the background to synthesize LabView code to an FPGA bitfile. With LabView, designers use the same development environment and language for all programmable targets in the heterogeneous computing system. The same language is used to express logic for processors and FPGAs. LabView is system design software that includes a graphical programming language based on structural dataflow. By its nature, it intuitively represents parallel functions and natively maps to the parallel implementation of logic in an FPGA and multicore processors. LabView abstracts the development of both processor and FPGA logic to the same language. With LabView, a single system designer can master the software and FPGA development realms that typically require two or more engineers with unique skills. An algorithm, once written, may be moved back and forth between processing and FPGA subsystems to optimize the system topology. The combination of processor, FPGA, and application-specific I/O programmed with LabView has defined the LabView RIO architecture. The Zynq-7000 All Programmable SoC embodies that architecture, and NI is working to support Zynq with LabView and future products based on Zynq technology. High-Level Tools, Off-the-Shelf Hardware, Shorter Time to MarketWith traditional approaches, I/O integration into an FPGA is often a time-consuming process. Many HLS tools cannot replace the entire HDL tool chain familiar to digital designers because the I/O interfaces from the FPGA fabric to the real world must still be implemented with HDL. Anecdotes from HDL design teams indicate that I/O integration often takes more than 70 percent of the time dedicated to design, while only 30 percent or less is spent adding differentiating value through control algorithms or signal processing. The LabView RIO architecture combines the LabView development language with a platform of off-the-shelf, FPGA-based hardware targets to minimize the time spent developing and integrating I/O. For example, all low-level SPI communication to an analog-to-digital converter, calibration, and conversion to fixed-point data are automatically implemented when using NI C Series I/O modules with NI CompactRIO hardware (Figure 3). The typical embedded system design team includes analog, digital, and mechanical engineers for hardware design; software developers for processor programming; and FPGA designers for HDL development. In addition, the team requires market or scientific domain experts who have the vertical industry knowledge of the application the design is going to fulfill. For example, a team working on a medical device may require a medical doctor. Individuals on large teams inherently have to communicate with other team members to ensure they are delivering the right elements to each other and staying on the same page. This larger team dynamic has a higher risk of miscommunication or misalignment during execution, leading to extra time to correct mistakes. LabView automatically implements and abstracts the low-level I/O integration details because NI design teams equip LabView with an awareness of all system components. The benefits of LabView system design software are best realized on NI-designed hardware targets. Smaller design teams find the tight integration of LabView software and FPGA-based hardware liberating—they are no longer burdened by the details of full custom design. They can spend more time focusing on adding their own value and differentiation and less on bringing up an operating system, developing middleware drivers, or debugging a PCB design signal integrity issue. Because LabView intuitively targets both the processor and programmable logic resources, market and scientific domain experts can play a more active role in developing rather than just consulting. When the domain experts implement directly, the results quickly match the scientific or market requirements (Figure 4). All programmable processors that include FPGA fabric deliver a flexible computing platform to replace many ASIC designs and augment traditional processor-centric designs. The additional reconfigurable programmable logic helps meet the challenges of extending product lifetimes while integrating new or evolving standards and adding highly parallel hardware-accelerated co-processing, and differentiating products with unique features. The biggest challenge with standardizing embedded system designs using both processing and programmable logic elements is the large gap between traditional development tools for the two subsystems. While silicon vendors continue to seek out ways to narrow that gap, smaller design teams can get to market faster with highly differentiated products using a system design approach based on off-the-shelf control and monitoring devices and LabView. National Instruments, Austin, TX. (512) 794-0100. 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