Embedded Systems Laboratory Director: Prof. David Atienza Alonso

Embedded Systems Laboratory Director: Prof. David Atienza Alonso http://esl.epfl.ch

Recent technological advances have pushed the integration potential to accommodate more functional units within a single unit area in state-of-the-art platforms. While managing to integrate more functional units, hence higher computing complexity assets, these new platforms could not attain high performance alongside high energy efficiency. This is indeed a surging requirement in the next-generation embedded platforms. The pursuit for high energy-efficient embedded computing platforms has explored many research directions in computing systems and circuits design. An emerging radical research direction exploits the inexactness of various microarchitectural components to achieve significant energy savings, by relaxing the correctness of these modules within acceptable. Recent works have demonstrated significant efficiency gains (multiplicative factor of 15), while degrading the quality with a relative error magnitude of 10% or less.

While the state-of-the-art has demonstrated inexact (or approximate) computing benefits at the circuit level, exploiting inexact computing at the system-level is still unexplored. In this project, we aim to exploit the inexactness of several microarchitectural components at the system-level targeting high-end multimedia and gaming applications. In particular, we aim to examine the mapping of prospective large-scale applications that are both data and computation intensive, on the next-generation embedded many-cores platform. The main target processor is the home-developed TAMARISC processing platform[1], which is shown in Figure 1. We will explore the inexactness of different microarchitectural blocks and leverage the inexactness to the ISA level. This is indeed an essential step to harness the profound impact inexactness would infer on the next-generation embedded platforms.

The student will:

1. 
   Study the architecture of the TAMARISC processor.
   
2. 
   Examine inexactness of the target microarchitectural blocks.
   
3. 
   Develop a behavioral description of inexactness at the core-level.
   
4. 
   Apply this behavioral description in a cycle-accurate SystemC simulation framework.
   
5. 
   Analyze the impact of inexactness on each of the TAMARISC instructions, running computational kernels (e.g. FFT, DCT).
   

1. 
   Good knowledge of C and SystemC programming and RTL design.
   
2. 
   Good understanding of computer organization.
   
3. 
   Interest in mapping applications to architecture platforms.