Micro Electronics & VLSI Internship- 2013 by Globals Technologies with 100% hands on Internship with live project experience in Banglore Head Office. Learn Semiconductor technology, Nmos, Pmos&Cmos logic, Designing Analog and Digital ICs,Analog Electronics and Digital Electronics, VLSI design procedure- Specification, Architecture, Layout design, Stick Design, Synthesis & Simulation, HDL modelling, VHDL programming, Verilog Programming, ASIC design, Testing& Verification of designs, Design on XILIN FPGA, System on Chip modelling, Hybrid applications with LABVIEW.
PHASE I :
Basic CMOS Theory
This module introduces the CMOS (Complementary Metal Oxide Semiconductor) circuits. MOS transistor theory and CMOS processing technology, circuit and logic design. Digital Logic Design
Digital Logic Design
This includes the study of Binary Systems, Boolean algebra and logic gates, Gate level minimization and combinational logic. It also includes Synchronous Sequential logic and Registers and counters.
• Simulation of Verilog HDL logic designs on Modelsim.
• Functional & formal verification of Verilog HDL designs.
• ASIC design in Verilog HDL.
• Implementing Digital Systems on XILINX FPGA board with Verilog HDL coding.
• Testing techniques of VHDL & Verilog HDL based designs.
• Mini Projects on verilog(Design and verification)
Content of L1 + L2 + L3 +
• Processors architecture & modeling.
• Digital Image Processing applications using VLSI.
• Digital Signal Processing applications using VLSI.
• System on chip modeling.
• Advanced FPGA design.
• Advanced testing and verification techniques.
• Hybrid applications with VLSI and LABView.
The module starts with the basic concepts of Verilog, modules and ports, Gate level modelling, DataFlow modelling, Behavioural modelling and the tasks and functions. The module also discusses about the Useful modelling techniques and timings and delays.
PHASE II –
This interesting subject deals with the Introduction to pipelining, pipeline hazards, how pipelining is implemented and what makes it so hard to implement pipelining. It also deals with extending of the MIPS pipeline to handle multicycle operations, crosscutting issues and the fallacies and pitfalls.
This brand new subject is a hot favourite. It deals with the Data types, operators and expressions, random constraint, Interprocess communication. It also deals with SystemVerilog clocking, program block, assertions, hierarchy and interface.
Two team-based industry standard projects en compassing RTL Design, Testbench Architecting, Testcase generation and Verification concepts to obtain a top level, hands-on view of VLSI Design and Verification.
More than 20 on/off-line seminars including:
3G WCDMA Technology.
SoC Design Considerations .
ANALOG AND DIGITAL COMMUNICATION
DTH Satellite Communication .
Information Security and Ethical Hacking
Broadband System and Router setup.
Embedded System .
.Net , PHP IT development and Research
Core JAVA & Advance JAVA .
GRID approach to Industry-Readiness
VinTrain takes pride in providing application-based approach to getting the trainees industry-ready by providing the Trainee (Students ) an indepth knowledge of: