UNIT-III DEPARTMENT OF INFORMATION TECHNIOLOGY::SVECW Page 13
HLLs can best be supported by optimizing performance of the most time-consuming
features of typical HLL programs.
• Generalizing from the work
of a number of researchers,
three elements emerge that,
by and large, characterize RISC architectures.
• First, use a large number of registers or use a compiler to optimize register usage. This is intended to optimize operand referencing. The studies just discussed show that there
are several references per HLL instruction and that there is a high proportion of move (assignment) statements. This suggests that performance can be improved by reducing memory references at the expense of more register references.
• Second, careful attention needs to be paid to the design of instruction pipelines. Because of the high proportion of conditional branch and
procedure call instructions, a straightforward instruction pipeline will be inefficient. This manifests itself as a high proportion of instructions that are prefetched but never executed.
• Finally, a simplified (reduced) instruction set is indicated. This point is
not as obvious as the others, but should become clearer in the ensuing discussion.
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