Artemis-2011-1 decision and platform support for model‐based eVolutionary development of Embedded systems Date of preparation

Purpose of WP1 is the definition of the requirements for tools and methodologies to be developed by the technology packages. Starting from the evaluation of the current state-of-the-art and state-of-practice approaches related to evolutionary development in the model-based engineering of embedded systems, requirements for tools and methodologies will be defined in order to provide: non-intrusive analysis and monitoring techniques to systematically collect information during the evolutions; decision support for the synthesis of system architectures; model management and visualization, to automate the management of models and improve comprehension during the system evolution. Safety and certification requirements will be also identified. WP1 is also responsible of the definition of test methodologies that will be applied during validation phase and the preliminary definition of candidate validation cases and scenarios.

This Task will accomplish the following activities:

Evaluation of commercial existing tools and European Patents

Evaluation of the needs about:

Learning from previous versions of the product

Hand-over of models to new engineering teams

Supporting product-management in steering the product requirements

Collect relevant and significant industry control use cases

This Task will accomplish the following activities:

Identification of the monitoring and analysis requirements for DECISIVE applications

Identification of the requirements for the definition of interfaces between DECISIVE models (high-level and analysis models, computation models, and platform specific execution models)

Identification of the requirements for human-centric tools able to provide better understanding of the systems

Requirements of a DECISIVE Human Interface Guideline able to define unambiguous systems requirements

Requirements cover model development perspectives - model editing, simulation, and analysis (with respect of model and result representation)

Identification of the requirements of indexes able to provide support to product management during the decision phase of evolutionary systems

Identification of requirement related to safety and certification features

T1.3 Test methodology definition

Lead: Philips

Contributors: Atego, CRF, IKER, MU, NXP-A, NXP-D, PHILIPS, UES

This Task will accomplish the following activities:

Find commonalities to ensure the reusability and cross-domain applicability of the DECISIVE methodology and tools

Preliminary definition of candidate validation cases and scenarios

Use cases reflecting the DECISIVE themes and provided by the industrial partners will be used to determine the most important data that have to be recorded and visualized during the system evolutions for support of an evolutionary design methodology. Details of requirements of this new approach will come from WP1. One of the key innovative elements in WP2 will be the extension to the current state-of-the-art modelling and design frameworks used by partners for the selected use cases to back-annotate the information learned during the system evolutions (Task 2.1 and 2.4). The second key element in WP2 is the provision of model-transformations that use information gained throughout the system evolutions to improve the quality of decisions, increase reuse, reduce the development time, increase the quality of the final implementation, improve the overall engineering process and support the creation of safety-cases (Task 2.2). The third key topic is efficient safety analysis, where WP2 studies the interplay between models and domain experts so that tools (computers) and experts (humans) can cooperate in the most efficient, flexible an cooperative manner (Task 2.3 and 2.4).

Thus WP2 covers the development and extensions of various modelling languages and the associated tools, and include the following:

Models for back-annotation (e.g. extension of SysML requirements diagrams, possibly extending the results of the ARTEMIS CHESS project)

Models for structured and modular system development, ranging from early stage languages for requirements elicitation to detailed design and implementation models (e.g. extensions to FBK’s languages for requirements and design analysis and validation, hierarchical extension of the CEA PsyC language for OASIS, extensions of SystemC for system descriptions towards VHDL/Verilog for physical implementation)

Models for safety analysis with focus on safety analysis in the early phases of development (e.g., extensions of the FSAP platform for safety analysis).

Techniques for model-driven design of user-interfaces, with a special focus on user interfaces for safety-critical systems

API's and data interfaces for provision of the monitoring and analysis results from WP3

System safety must be considered from the very start of the project. It is thus important that all the formalisms and models used in the project are able to support safety analysis in an efficient way. The problems and challenges in this area are related both to modelling language – what can be expressed – and to the methods used for safety analysis – how can we use the information presented by the model in the most efficient way?

T2.1 Development of extensions to existing models and languages

Lead: xx

Contributors: CISC, CEA, TEC, NXP-D, FBK

ATEGO (x PM): will work on:

1. 
   Integration of safety standards and the corresponding analyses in the infrastructure (focus on 26262 automotive standard norm).
   
2. 
   Integration of OASIS to guarantee time and space isolation in the early stages of model-based engineering development
   
3. 
   Results of safety analyses and OASIS should be provided at modeling level.
   
4. 
   Study of mechanisms to preserve safety properties under compositionality and composability
   
5. 
   Development of a prototype in Artisan Studio to support the DECISIVE results
   

1. 
   Development of a hierarchical extension of the PsyC language (OASIS programming language) in order to allow compositional design directly in PsyC and in connection with higher-level models
   
2. 
   Implementation of the mechanisms for model annotation and extraction of information to be back-annotated into higher-level models and provided to analysis and decision-aid tools
   

NXP-D (12 PM): will use results from earlier projects and product developments to introduce new behavioural and functional aspects to improve those as well as the new target architecture. Special focus will be on the modularity and scalability of those models to increase the possible re-use and allow faster adoption to new architectures. In conjunction with task T2.4 flexibility shall be gained to combine building blocks from already existing systems with new system components.

1. 
   Access existing concepts and their key strengths or disadvantages
   
2. 
   Identify what can be reused for a next-level modelling style and framework, what extensions are required to gain above mentioned flexibility
   

Lead: FBK

Contributors: FBK

ATEGO(x PM): will work on:

1. 
   Implementation of the engineering techniques to automate safety analyses
   
2. 
   Contribution on methodological aspects
   
3. 
   Contribution on coherence between high-level and low-level specification with respect to safety properties
   
4. 
   Development of a prototype in Artisan Studio to support the DECISIVE results
   

Lead: xx

Contributors . TEC, FBK

This task is based on the output of T2.2, and will provide:

1. 
   templates and techniques for specifying safety requirements. Here we will also build on and extend the work on requirements boilerplates from the ARTEMIS project CESAR
   
2. 
   ontology-based support for analyzing completeness, consistency and standard compliance of safety requirements
   

FBK (x PM): Extension and integration of FBK’s tools and techniques for early validation of functional requirements analyzing their consistency, completeness and correctness.

T2.4 Model-based development of user interfaces

Lead: CISC

Contributors: CISC, NXP-D

CISC (12 PM): extension of the existing user interface within tool System Architect Designer (SyAD®) to extend the automatic generation of test benches for Black and White-Box testing based on SystemC (TLM) with focus on DECISIVE applications. In particular this will be a “Use Case” editor, design variants/configuration support, support of analogue modelling with SystemC-AMS.

NXP-D (12PM): will investigate the possibilities to extend the abstraction levels to allow modelling and simulation of building blocks of different complexity. To even better represent performance parameters of new models the simulation should be extendable real time emulation input. The hierarchy level of models to be used will span from re-used functional blocks, for which complete characterization results will be available, up to high level models described on pure algorithmic level (e.g. SystemC, FPGA based real-time simulation ), totally independent of the technology used later. Further the heterogeneity of the architecture, consisting of as well digital, analog as well as sensory and other elements, must be fully reflected by used tools and modelling framework.

WP3 plays an important role in the overall workflow of DECISIVE represented by the technical work packages.

Within this work package the needed evaluation, simulation, mining and profiling techniques will be developed to generate and analyse data for the characterization of software/hardware components in respect to their runtime behaviour, memory footprint, power consumption, etc. This data will be used at runtime and design time of a software component. For reusing this information during the evolution of components it will be back annotated to the high-level model description (cf. WP2).

In that sense WP3 covers the development of techniques, which can be distinguished by the time when they will be applied:

At design time the developer of a software component typically uses simulation and profiling techniques to debug, validate and optimise a given component. Here it will be necessary to implement a framework for the model-based analysis and design of distributed systems. This framework can also incorporate middleware architectures in respect to their RT behaviour, which will be the high level simulation approach within the project. To support model-based analysis techniques with exact results it is needed to implement a low level profiling methodology. This methodology must be able to profile a complete system platform constructed of software and hardware components. The hardware components typically represent the execution platform of a software component. The methodology needs to be completely independent from the underlying architecture of the execution platform in order to support a wide variety of systems, e.g. simple single-processor embedded systems as well network on chip architectures.

To gather timing information of the runtime behaviour of a software component it is needed to develop monitoring infrastructures, which are ideally integrated in the kernel of the underlying operating system/runtime system. This information can be used for example for optimising RT scheduling mechanisms. For supporting software monitoring mechanisms integrated in the operating/runtime system hardware monitors are needed, which allow non-intrusively gathering of the profiling data. The monitoring infrastructures need to be as generic as possible in order to guarantee a unified approach across the different applications and measurements. In particular we want to achieve better usage of performance counters during execution. Simulation and process mining techniques are used to provide detailed information about the dynamic behaviour of the platform and its performance. Several different aspects of performance metrics will be important, both those traditionally focused on (e.g. speed and memory consumption) and also additional metrics such as power consumption, which have recently seen increasing interest in response to energy and climate challenges as well as in the field of mobile devices. Hence, it is interesting to look into the use of performance counters and other HW-assisted monitors to estimate energy consumption.

Design and runtime methodologies generate massive amounts of data, which need to be managed and processed in a way, that the designer can use the information in a fast and efficient way. For that purpose WP3 will not only focus on the generation of analysis information, but as well on post-processing and database concepts for that special purpose. Note that we will analyze the embedded systems deployed in the field. For the analysis of the enormous amount of data we will use and develop process mining techniques. These techniques automatically construct models that can be used to understand the dynamic behavior and to suggest improvements. Note that an increasing number of embedded systems is connected to the internet. See for example the medical equipment of Philips Healthcare and the lithography systems of ASML that are collecting detailed event logs. These logs can be used for remote diagnostics based on process mining. For example, it can be predicted whether a machine will fail, why it fails, and how it can be repaired.

T3.1 Runtime and simulation monitoring

Lead: Philips

Contributors: CEA, Philips, TUE

CEA: will develop and implement the monitoring support for its safety-oriented real-time operating platform OASIS. This platform comprises the following elements

A programming language PsyC – an extension of C – that allows to design applications with explicit parallel architecture, structured as a collection of agents communicating through dataflow and message passing. Furthermore, all elements of an OASIS application – agent behaviour and communication – have explicit temporal properties.

Several implementations of the OASIS kernel responsible for managing temporal behavior of the application and communications between the agents.

Kernel implementations exist for various environments: POSIX execution and simulation on Linux platforms, and native execution on several bare-bone architectures (IA32, ARM7, ARM9 and several others). Typical OASIS applications target embedded execution and, therefore, information such as execution time, power consumption, frequency of inter-core migrations or code-coverage is very important for system sizing and optimization. We expect the DECISIVE results to allow collecting such information through application monitoring without considerable impact on system performance. System support for such monitoring will provide means (e.g. API, but could be something more complete to enable periodic – off-line? – information collection) to integrate the collected information into the models used at design time for analysis. This latter functionality provides a link with WP2.

Philips: Philips Healthcare iXR will contribute via the design of a diagnostic infrastructure. This infrastructure consists of monitoring software for both the X-ray acquisition hardware as well as the PC-based infrastructure that controls them. The infrastructure collects this information, provides mechanisms to draw conclusions, and makes it available remotely.

Lead: Philips

T3.3 Profiling based analysis and simulation techniques

Focusing on the run-time characterization of system platforms in respect to power consumption, processing performance and real-time behavior it is expected that conventional or state of the art profiling and simulation techniques cannot be used for the task of analyzing and profiling. Especially profiling memory accesses on a cycle accurate basis is not or not sufficiently supported by available profiling tools and methodologies due to the fact that in most cases only shared memory architectures were modeled at the time. With the emerging trend building embedded systems based upon multi core and many core architectures with completely different connection topologies it is foreseen that new profiling techniques will be required which take as well the actual connection topology into account. Based on the profiling methodologies it will be possible to get an in depth view of how programming models and runtime systems behave on enhanced embedded processor platforms, which can consist of more than one processor core. The results can be used to co-optimize the runtime system, programming model and the architecture of the computing platform.

FHG-HHI: HHI will work on system level profiling methodologies using System C platform descriptions which can be used for run-time characterization of system platforms in respect to power consumption, processing performance and real-time behavior
To achieve precise results in respect to the real-time behavior of a given system FHG-HHI will develop a non intrusive profiling and exploration methodology, which is suited for platform models implemented using the modeling language SystemC. Instead of manually instrumenting the SystemC code of a multi core platform or a similar architecture itself, the methodology relies on the architecture elaboration phase of a SystemC compilation run. After the specific elaboration phase the actual architecture under investigation will be visualized and can be prepared for a simulation run by adding probes for data types, busses, program counters, etc. which should be observed by the profiler. The methodology will support simple SystemC constructs as well as complex TLM2.0 based architectures. The data collected by the so called backend tool will be visualized by a corresponding frontend, which will be integrated into an existing state of the art design flow. The same frontend could also be able to collect and visualize data that has been gathered by the hardware monitoring service described in task T3.4.

According to the given terminology the tool will be used during the design time of an embedded system for simulation, profiling and HW/SW co- exploration.

Deliverables:

D3.3.1 Use case analysis and specification of analysis and profiling methodologies

The document will review state of the art profiling methodologies and will highlight missing features in respect to special use cases. Based on the results of the use case analysis a detailed specification will be defined, which will be the basis for the implementation of the tools delivered in D3.3.2.

D3.3.2 Tool chain consisting of profiling and post processing tools (Type : Prototype)

The deliverable will consist of running prototypes of the tools as defined in D3.3.1. including an appropriate written documentation.

Lead: FHG-HHI

Contributors: FHG-HHI, NXP-A, NXP-D

For system wide tuning and observation of runtime metrics e.g. core clock frequency, memory allocation, heap size, real time -behavior and –violations it is essential to collect corresponding information of the system at runtime. Due to the fact, those e.g. monitoring memory access transactions can result in very high computational demands, it is needed to have specialized hardware monitoring features in the system architecture, which will be accessible by external debugging tools and the system itself for automatic runtime optimization.

In contrast to the methodology described in task T3.3 the monitoring system will be used at runtime, but will be compatible with the developed data visualization front end of task T3.3.